diff options
| author | Ira Weiny <ira.weiny@intel.com> | 2022-12-14 12:54:11 -0800 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2022-12-21 07:32:24 -0500 |
| commit | 617564bf92cfc809fd50026c087c617d0e721f4c (patch) | |
| tree | 32ac516b2c5e387a24e6486f916b0df04d9f4d35 /hw | |
| parent | fbae27e857061e1098c21944c81bd025c8946c62 (diff) | |
hw/cxl/device: Add Flex Bus Port DVSEC
The Flex Bus Port DVSEC was missing on type 3 devices which was blocking
RAS checks.[1]
Add the Flex Bus Port DVSEC to type 3 devices as per CXL 3.0 8.2.1.3.
[1] https://lore.kernel.org/linux-cxl/167096738875.2861540.11815053323626849940.stgit@djiang5-desk3.ch.intel.com/
Cc: Dave Jiang <dave.jiang@intel.com>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Ben Widawsky <bwidawsk@kernel.org>
Cc: qemu-devel@nongnu.org
Cc: linux-cxl@vger.kernel.org
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Message-Id: <20221213-ira-flexbus-port-v2-1-eaa48d0e0700@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/mem/cxl_type3.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 255590201a..dae4fd89ca 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -295,6 +295,17 @@ static void build_dvsecs(CXLType3Dev *ct3d) cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE, GPF_DEVICE_DVSEC_LENGTH, GPF_DEVICE_DVSEC, GPF_DEVICE_DVSEC_REVID, dvsec); + + dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){ + .cap = 0x26, /* 68B, IO, Mem, non-MLD */ + .ctrl = 0x02, /* IO always enabled */ + .status = 0x26, /* same as capabilities */ + .rcvd_mod_ts_data_phase1 = 0xef, /* WTF? */ + }; + cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE, + PCIE_FLEXBUS_PORT_DVSEC_LENGTH_2_0, + PCIE_FLEXBUS_PORT_DVSEC, + PCIE_FLEXBUS_PORT_DVSEC_REVID_2_0, dvsec); } static void hdm_decoder_commit(CXLType3Dev *ct3d, int which) |