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authorBALATON Zoltan <balaton@eik.bme.hu>2017-08-20 19:23:05 +0200
committerDavid Gibson <david@gibson.dropbear.id.au>2017-09-08 09:30:55 +1000
commit97c2acb5504ee0ab0a5efc39a06f9783220dba90 (patch)
tree8e2294dff2e58fc47e14b7c3f7e34b35cb2265a4 /hw
parent44a935d8c3f09089e740a89b5af5d71c134b93df (diff)
ppc4xx: Export ECB and PLB emulation
Make these device models available outside ppc405_uc.c for reuse in 460EX emulation. They are left in their current place for now because they are used mostly unchanged and I'm not sure these correctly model the components in 440 SoCs (but they seem to be good enough). These functions could be moved in a subsequent clean up series when this is confirmed. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw')
-rw-r--r--hw/ppc/ppc405.h3
-rw-r--r--hw/ppc/ppc405_uc.c4
2 files changed, 5 insertions, 2 deletions
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index a9ffc87f19..7ed25cfa1b 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -59,6 +59,9 @@ struct ppc4xx_bd_info_t {
ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
uint32_t flags);
+void ppc4xx_plb_init(CPUPPCState *env);
+void ppc405_ebc_init(CPUPPCState *env);
+
CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[4],
hwaddr ram_bases[4],
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 8f44cb46d0..e621d0aec5 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -174,7 +174,7 @@ static void ppc4xx_plb_reset (void *opaque)
plb->besr = 0x00000000;
}
-static void ppc4xx_plb_init(CPUPPCState *env)
+void ppc4xx_plb_init(CPUPPCState *env)
{
ppc4xx_plb_t *plb;
@@ -585,7 +585,7 @@ static void ebc_reset (void *opaque)
ebc->cfg = 0x80400000;
}
-static void ppc405_ebc_init(CPUPPCState *env)
+void ppc405_ebc_init(CPUPPCState *env)
{
ppc4xx_ebc_t *ebc;