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authorAleksandr Bezzubikov <zuban32s@gmail.com>2017-08-18 02:36:48 +0300
committerMichael S. Tsirkin <mst@redhat.com>2017-09-08 16:15:17 +0300
commit70e1ee59bb9490d9ac529e96820a03b346086ca1 (patch)
tree79d1ed786bcbdefd36bb950666de67ca796191e4 /hw
parenta35fe226558ac85436ea01af8977f1834927f53f (diff)
hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware
On PCI init PCI bridges may need some extra info about bus number, IO, memory and prefetchable memory to reserve. QEMU can provide this with a special vendor-specific PCI capability. Signed-off-by: Aleksandr Bezzubikov <zuban32s@gmail.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Tested-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/pci/pci_bridge.c46
1 files changed, 46 insertions, 0 deletions
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
index 720119b21a..17feae5ed8 100644
--- a/hw/pci/pci_bridge.c
+++ b/hw/pci/pci_bridge.c
@@ -408,6 +408,52 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
br->bus_name = bus_name;
}
+
+int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
+ uint32_t bus_reserve, uint64_t io_reserve,
+ uint32_t mem_non_pref_reserve,
+ uint32_t mem_pref_32_reserve,
+ uint64_t mem_pref_64_reserve,
+ Error **errp)
+{
+ if (mem_pref_32_reserve != (uint32_t)-1 &&
+ mem_pref_64_reserve != (uint64_t)-1) {
+ error_setg(errp,
+ "PCI resource reserve cap: PREF32 and PREF64 conflict");
+ return -EINVAL;
+ }
+
+ if (bus_reserve == (uint32_t)-1 &&
+ io_reserve == (uint64_t)-1 &&
+ mem_non_pref_reserve == (uint32_t)-1 &&
+ mem_pref_32_reserve == (uint32_t)-1 &&
+ mem_pref_64_reserve == (uint64_t)-1) {
+ return 0;
+ }
+
+ size_t cap_len = sizeof(PCIBridgeQemuCap);
+ PCIBridgeQemuCap cap = {
+ .len = cap_len,
+ .type = REDHAT_PCI_CAP_RESOURCE_RESERVE,
+ .bus_res = bus_reserve,
+ .io = io_reserve,
+ .mem = mem_non_pref_reserve,
+ .mem_pref_32 = mem_pref_32_reserve,
+ .mem_pref_64 = mem_pref_64_reserve
+ };
+
+ int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,
+ cap_offset, cap_len, errp);
+ if (offset < 0) {
+ return offset;
+ }
+
+ memcpy(dev->config + offset + PCI_CAP_FLAGS,
+ (char *)&cap + PCI_CAP_FLAGS,
+ cap_len - PCI_CAP_FLAGS);
+ return 0;
+}
+
static const TypeInfo pci_bridge_type_info = {
.name = TYPE_PCI_BRIDGE,
.parent = TYPE_PCI_DEVICE,