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authorPhilippe Mathieu-Daudé <philmd@linaro.org>2024-02-13 08:31:45 +0100
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2024-02-15 16:58:46 +0100
commite6097f186416df368a7f87a37f0a7fd25de587ba (patch)
tree549924fa2ed0c04c1db0084c754a873b23cf880d /hw
parent41c05b41e3b3c5b6b167c315d0f25eb355dcc326 (diff)
hw/ide/ahci: Inline ahci_get_num_ports()
Introduce the 'ich9' variable and inline ahci_get_num_ports(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240213081201.78951-5-philmd@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/i386/pc_q35.c6
-rw-r--r--hw/ide/ahci.c8
-rw-r--r--hw/mips/boston.c6
3 files changed, 8 insertions, 12 deletions
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index a89f900c4c..09e12418f9 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -292,16 +292,18 @@ static void pc_q35_init(MachineState *machine)
if (pcms->sata_enabled) {
PCIDevice *pdev;
+ AHCIPCIState *ich9;
/* ahci and SATA device, for q35 1 ahci controller is built-in */
pdev = pci_create_simple_multifunction(host_bus,
PCI_DEVFN(ICH9_SATA1_DEV,
ICH9_SATA1_FUNC),
"ich9-ahci");
+ ich9 = ICH9_AHCI(pdev);
idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0");
idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1");
- g_assert(MAX_SATA_PORTS == ahci_get_num_ports(pdev));
- ide_drive_get(hd, ahci_get_num_ports(pdev));
+ g_assert(MAX_SATA_PORTS == ich9->ahci.ports);
+ ide_drive_get(hd, ich9->ahci.ports);
ahci_ide_create_devs(pdev, hd);
} else {
idebus[0] = idebus[1] = NULL;
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index aa9381a7b2..8b97c6b0e7 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -1896,14 +1896,6 @@ static void sysbus_ahci_register_types(void)
type_init(sysbus_ahci_register_types)
-int32_t ahci_get_num_ports(PCIDevice *dev)
-{
- AHCIPCIState *d = ICH9_AHCI(dev);
- AHCIState *ahci = &d->ahci;
-
- return ahci->ports;
-}
-
void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd)
{
AHCIPCIState *d = ICH9_AHCI(dev);
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 0ec0b98066..a6c7bc18ff 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -678,6 +678,7 @@ static void boston_mach_init(MachineState *machine)
MemoryRegion *sys_mem = get_system_memory();
XilinxPCIEHost *pcie2;
PCIDevice *pdev;
+ AHCIPCIState *ich9;
DriveInfo *hd[6];
Chardev *chr;
int fw_size, fit_err;
@@ -771,8 +772,9 @@ static void boston_mach_init(MachineState *machine)
pdev = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus,
PCI_DEVFN(0, 0), TYPE_ICH9_AHCI);
- g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(pdev));
- ide_drive_get(hd, ahci_get_num_ports(pdev));
+ ich9 = ICH9_AHCI(pdev);
+ g_assert(ARRAY_SIZE(hd) == ich9->ahci.ports);
+ ide_drive_get(hd, ich9->ahci.ports);
ahci_ide_create_devs(pdev, hd);
if (machine->firmware) {