diff options
| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2014-01-06 10:16:39 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-01-08 19:07:21 +0000 |
| commit | 11a239a51ccbf27a22e2aa5f423ff1d6f5df65a7 (patch) | |
| tree | 0a6aa44475858b141a783d52f887db6332f358cc /hw | |
| parent | 676f4c095d53841626b1ee2cbc7a53b4f6239e4e (diff) | |
char/cadence_uart: Define Missing SR/ISR fields
Some (interrupt) status register bits relating to the TxFIFO path were
not defined. Define them. This prepares support for proper Tx data path
flow control.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 2068b963f0af8cc834c353944e9fa816d950b163.1388626249.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/char/cadence_uart.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index ddd7267259..216eed7442 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -34,6 +34,9 @@ #define UART_SR_INTR_RFUL 0x00000004 #define UART_SR_INTR_TEMPTY 0x00000008 #define UART_SR_INTR_TFUL 0x00000010 +/* somewhat awkwardly, TTRIG is misaligned between SR and ISR */ +#define UART_SR_TTRIG 0x00002000 +#define UART_INTR_TTRIG 0x00000400 /* bits fields in CSR that correlate to CISR. If any of these bits are set in * SR, then the same bit in CISR is set high too */ #define UART_SR_TO_CISR_MASK 0x0000001F @@ -43,6 +46,7 @@ #define UART_INTR_PARE 0x00000080 #define UART_INTR_TIMEOUT 0x00000100 #define UART_INTR_DMSI 0x00000200 +#define UART_INTR_TOVR 0x00001000 #define UART_SR_RACTIVE 0x00000400 #define UART_SR_TACTIVE 0x00000800 |