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authorAnthony Liguori <aliguori@us.ibm.com>2013-03-22 13:05:57 -0500
committerAnthony Liguori <aliguori@us.ibm.com>2013-03-22 13:05:57 -0500
commitcecd77ae6df060bbe8f0eea6691112097e680a52 (patch)
tree4c82bcf59884c6555cb0199a1f96a26a2dfaf83a /hw
parentf9308207040dc4a1484cee459bedaec03645b935 (diff)
parent01ed1d527c59356e6c4c9d54b5710a3c9e78ce4e (diff)
Merge remote-tracking branch 'stefanha/trivial-patches' into staging
# By liguang (2) and others # Via Stefan Hajnoczi * stefanha/trivial-patches: qdev: remove redundant abort() gitignore: ignore more files Use proper term in TCG README serial: Fix debug format strings Fix typos and misspellings Advertise --libdir in configure --help output memory: fix a bug of detection of memory region collision MinGW: Replace setsockopt by qemu_setsocketopt
Diffstat (limited to 'hw')
-rw-r--r--hw/arm-misc.h2
-rw-r--r--hw/pci/pci_host.c2
-rw-r--r--hw/qdev.c3
-rw-r--r--hw/sdhci.c2
-rw-r--r--hw/serial.c4
5 files changed, 6 insertions, 7 deletions
diff --git a/hw/arm-misc.h b/hw/arm-misc.h
index cba7553039..7b2b02daaf 100644
--- a/hw/arm-misc.h
+++ b/hw/arm-misc.h
@@ -14,7 +14,7 @@
#include "exec/memory.h"
#include "hw/irq.h"
-/* The CPU is also modeled as an interrupt controller. */
+/* The CPU is also modelled as an interrupt controller. */
#define ARM_PIC_CPU_IRQ 0
#define ARM_PIC_CPU_FIQ 1
qemu_irq *arm_pic_init_cpu(ARMCPU *cpu);
diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c
index daca1c1ea0..12254b18a9 100644
--- a/hw/pci/pci_host.c
+++ b/hw/pci/pci_host.c
@@ -38,7 +38,7 @@ do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0)
* bit 0 - 7: offset in configuration space of a given pci device
*/
-/* the helper functio to get a PCIDeice* for a given pci address */
+/* the helper function to get a PCIDevice* for a given pci address */
static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr)
{
uint8_t bus_num = addr >> 16;
diff --git a/hw/qdev.c b/hw/qdev.c
index 0b20280133..708a058a91 100644
--- a/hw/qdev.c
+++ b/hw/qdev.c
@@ -117,11 +117,10 @@ DeviceState *qdev_create(BusState *bus, const char *name)
if (bus) {
error_report("Unknown device '%s' for bus '%s'", name,
object_get_typename(OBJECT(bus)));
- abort();
} else {
error_report("Unknown device '%s' for default sysbus", name);
- abort();
}
+ abort();
}
return dev;
diff --git a/hw/sdhci.c b/hw/sdhci.c
index 93feada049..4a29e6cf7f 100644
--- a/hw/sdhci.c
+++ b/hw/sdhci.c
@@ -763,7 +763,7 @@ static void sdhci_do_adma(SDHCIState *s)
}
}
- /* we have unfinished bussiness - reschedule to continue ADMA */
+ /* we have unfinished business - reschedule to continue ADMA */
qemu_mod_timer(s->transfer_timer,
qemu_get_clock_ns(vm_clock) + SDHC_TRANSFER_DELAY);
}
diff --git a/hw/serial.c b/hw/serial.c
index 48a5eb62b9..0ccc499285 100644
--- a/hw/serial.c
+++ b/hw/serial.c
@@ -306,7 +306,7 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
SerialState *s = opaque;
addr &= 7;
- DPRINTF("write addr=0x%02x val=0x%02x\n", addr, val);
+ DPRINTF("write addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 "\n", addr, val);
switch(addr) {
default:
case 0:
@@ -527,7 +527,7 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
ret = s->scr;
break;
}
- DPRINTF("read addr=0x%02x val=0x%02x\n", addr, ret);
+ DPRINTF("read addr=0x%" HWADDR_PRIx " val=0x%02x\n", addr, ret);
return ret;
}