diff options
| author | BALATON Zoltan <balaton@eik.bme.hu> | 2023-07-19 02:32:55 +0200 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2023-08-04 10:50:19 -0300 |
| commit | aa1133475e0fdea0ab7d994c0a62b74d575cfcce (patch) | |
| tree | db29cb9f061330b50c0a2bde2c232042416c1cf8 /hw | |
| parent | 19ac7b29f81196dc20c9d97cf36f9004fa7e60c4 (diff) | |
ppc/pegasos2: Fix reg property of ROM BARs
The register offset of the ROM BAR is 0x30 not 0x28. This fixes the
reg property entry of the ROM region in the device tree.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-ID: <6abd73b1211f9d0776dfa5d71d6294f17eecb426.1689725688.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/ppc/pegasos2.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index 4a2ab35f19..8ed13a42a2 100644 --- a/hw/ppc/pegasos2.c +++ b/hw/ppc/pegasos2.c @@ -766,7 +766,11 @@ static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque) if (!d->io_regions[i].size) { continue; } - cells[j] = cpu_to_be32(d->devfn << 8 | (PCI_BASE_ADDRESS_0 + i * 4)); + cells[j] = PCI_BASE_ADDRESS_0 + i * 4; + if (cells[j] == 0x28) { + cells[j] = 0x30; + } + cells[j] = cpu_to_be32(d->devfn << 8 | cells[j]); if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { cells[j] |= cpu_to_be32(1 << 24); } else { |