diff options
| author | Paolo Bonzini <pbonzini@redhat.com> | 2013-03-05 15:04:36 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2014-05-13 13:22:29 +0200 |
| commit | 4700a316df7d2cdcd256dcd64a10cec643f4dfa1 (patch) | |
| tree | f51f9f50e9514558cc4d7cc9a166968596eabfbd /hw | |
| parent | 4a92a558f49cb0693e36bd6d4f9217f298045be2 (diff) | |
pc: port 92 reset requires a low->high transition
The PIIX datasheet says that "before another INIT pulse can be
generated via [port 92h], [bit 0] must be written back to a
zero.
This bug is masked right now because a full reset will clear the
value of port 92h. But once we implement soft reset correctly,
the next attempt to enable the A20 line by setting bit 1 (and
leaving the others untouched) will cause another reset.
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/i386/pc.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 07de2384ad..e6369d5be6 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -471,11 +471,12 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { Port92State *s = opaque; + int oldval = s->outport; DPRINTF("port92: write 0x%02x\n", val); s->outport = val; qemu_set_irq(*s->a20_out, (val >> 1) & 1); - if (val & 1) { + if ((val & 1) && !(oldval & 1)) { qemu_system_reset_request(); } } |