aboutsummaryrefslogtreecommitdiff
path: root/hw
diff options
context:
space:
mode:
authorRichard Henderson <richard.henderson@linaro.org>2022-05-28 08:19:07 -0700
committerRichard Henderson <richard.henderson@linaro.org>2022-05-28 08:19:07 -0700
commit0234342e0ea9411ad032dac61f3d632536bda789 (patch)
treee7b2fa3f30d4ba4e0c2e55668d19232793a0b996 /hw
parent272be013d3d3a3218ea7800c579d0e144da679ca (diff)
parent5079892df5f113c7f2b77f53bf7663f6c7bc6be9 (diff)
Merge tag 'hppa-serial-fix-pull-request' of https://github.com/hdeller/qemu-hppa into staging
hppa: Fix serial port pass-through This series fixes the SeaBIOS-hppa firmware and the serial ports setup code in qemu so that it reflects the real hardware and allows serial port pass-through from the host to guests. Tested with Linux guests. v2: Changes suggested by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> - Split out hppa_hardware.h restoration to an own patch - Drop unneccesary checks for serial_hd(x) Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCYpH5NAAKCRD3ErUQojoP # X0p3APsHdN4SDIVHJ3vjfzrvmuJ8rEUzsK4COdlgWBUT4jgVBgEApk9jj6X0ZfkI # bUVVQAOqHZbgXhEeiHNVWbsPfEqsqQw= # =aj8q # -----END PGP SIGNATURE----- # gpg: Signature made Sat 28 May 2022 03:28:04 AM PDT # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * tag 'hppa-serial-fix-pull-request' of https://github.com/hdeller/qemu-hppa: hppa: Fix serial port assignments and pass-through hppa: Sync contents of hppa_hardware.h header file with SeaBIOS-hppa New SeaBIOS-hppa version 6 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/hppa/hppa_hardware.h10
-rw-r--r--hw/hppa/machine.c22
2 files changed, 16 insertions, 16 deletions
diff --git a/hw/hppa/hppa_hardware.h b/hw/hppa/hppa_hardware.h
index 8b6b9222cb..a5ac3dd0fd 100644
--- a/hw/hppa/hppa_hardware.h
+++ b/hw/hppa/hppa_hardware.h
@@ -1,4 +1,5 @@
/* HPPA cores and system support chips. */
+/* Be aware: QEMU and seabios-hppa repositories share this file as-is. */
#ifndef HW_HPPA_HPPA_HARDWARE_H
#define HW_HPPA_HPPA_HARDWARE_H
@@ -30,13 +31,18 @@
#define PCI_HPA DINO_HPA /* PCI bus */
#define IDE_HPA 0xf9000000 /* Boot disc controller */
+/* offsets to DINO HPA: */
+#define DINO_PCI_ADDR 0x064
+#define DINO_CONFIG_DATA 0x068
+#define DINO_IO_DATA 0x06c
+
#define PORT_PCI_CMD (PCI_HPA + DINO_PCI_ADDR)
#define PORT_PCI_DATA (PCI_HPA + DINO_CONFIG_DATA)
#define FW_CFG_IO_BASE 0xfffa0000
-#define PORT_SERIAL1 (DINO_UART_HPA + 0x800)
-#define PORT_SERIAL2 (LASI_UART_HPA + 0x800)
+#define PORT_SERIAL1 (LASI_UART_HPA + 0x800)
+#define PORT_SERIAL2 (DINO_UART_HPA + 0x800)
#define HPPA_MAX_CPUS 16 /* max. number of SMP CPUs */
#define CPU_CLOCK_MHZ 250 /* emulate a 250 MHz CPU */
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index d1e174b1f4..63b9dd2396 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -32,7 +32,7 @@
#define MAX_IDE_BUS 2
-#define MIN_SEABIOS_HPPA_VERSION 1 /* require at least this fw version */
+#define MIN_SEABIOS_HPPA_VERSION 6 /* require at least this fw version */
#define HPA_POWER_BUTTON (FIRMWARE_END - 0x10)
@@ -236,20 +236,14 @@ static void machine_hppa_init(MachineState *machine)
/* Realtime clock, used by firmware for PDC_TOD call. */
mc146818_rtc_init(isa_bus, 2000, NULL);
- /* Serial code setup. */
- if (serial_hd(0)) {
- uint32_t addr = DINO_UART_HPA + 0x800;
- serial_mm_init(addr_space, addr, 0,
- qdev_get_gpio_in(dino_dev, DINO_IRQ_RS232INT),
- 115200, serial_hd(0), DEVICE_BIG_ENDIAN);
- }
+ /* Serial ports: Lasi and Dino use a 7.272727 MHz clock. */
+ serial_mm_init(addr_space, LASI_UART_HPA + 0x800, 0,
+ qdev_get_gpio_in(lasi_dev, LASI_IRQ_UART_HPA), 7272727 / 16,
+ serial_hd(0), DEVICE_BIG_ENDIAN);
- if (serial_hd(1)) {
- /* Serial port */
- serial_mm_init(addr_space, LASI_UART_HPA + 0x800, 0,
- qdev_get_gpio_in(lasi_dev, LASI_IRQ_UART_HPA), 8000000 / 16,
- serial_hd(1), DEVICE_BIG_ENDIAN);
- }
+ serial_mm_init(addr_space, DINO_UART_HPA + 0x800, 0,
+ qdev_get_gpio_in(dino_dev, DINO_IRQ_RS232INT), 7272727 / 16,
+ serial_hd(1), DEVICE_BIG_ENDIAN);
/* Parallel port */
parallel_mm_init(addr_space, LASI_LPT_HPA + 0x800, 0,