diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-07-06 16:19:21 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-07-06 16:19:21 +0100 |
| commit | 822cb97cefe2416ce61fe8007ad69904bbe24502 (patch) | |
| tree | 8bcf63d80916eb7d2a3e46d82c405fb2426db952 /hw | |
| parent | 0618e72d64e434dd6f1bc38b107670474c49fb86 (diff) | |
| parent | c41077235168140cdd4a34fce9bd95c3d30efe9c (diff) | |
Merge tag 'pull-target-arm-20230706' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Add raw_writes ops for register whose write induce TLB maintenance
* hw/arm/sbsa-ref: use XHCI to replace EHCI
* Avoid splitting Zregs across lines in dump
* Dump ZA[] when active
* Fix SME full tile indexing
* Handle IC IVAU to improve compatibility with JITs
* xlnx-canfd-test: Fix code coverity issues
* gdbstub: Guard M-profile code with CONFIG_TCG
* allwinner-sramc: Set class_size
* target/xtensa: Assert that interrupt level is within bounds
* Avoid over-length shift in arm_cpu_sve_finalize() error case
* Define new 'neoverse-v1' CPU type
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# gpg: Signature made Thu 06 Jul 2023 02:23:13 PM BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
* tag 'pull-target-arm-20230706' of https://git.linaro.org/people/pmaydell/qemu-arm:
target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case
target/arm: Define neoverse-v1
target/arm: Suppress more TCG unimplemented features in ID registers
target/xtensa: Assert that interrupt level is within bounds
hw: arm: allwinner-sramc: Set class_size
target/arm: gdbstub: Guard M-profile code with CONFIG_TCG
tests/qtest: xlnx-canfd-test: Fix code coverity issues
target/arm: Handle IC IVAU to improve compatibility with JITs
target/arm: Fix SME full tile indexing
target/arm: Dump ZA[] when active
target/arm: Avoid splitting Zregs across lines in dump
tests/tcg/aarch64/sysregs.c: Use S syntax for id_aa64zfr0_el1 and id_aa64smfr0_el1
hw/arm/sbsa-ref: use XHCI to replace EHCI
target/arm: Add raw_writes ops for register whose write induce TLB maintenance
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/arm/Kconfig | 2 | ||||
| -rw-r--r-- | hw/arm/sbsa-ref.c | 24 | ||||
| -rw-r--r-- | hw/arm/virt.c | 1 | ||||
| -rw-r--r-- | hw/misc/allwinner-sramc.c | 1 |
4 files changed, 17 insertions, 11 deletions
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7de17d1e8c..7e68348440 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -266,7 +266,7 @@ config SBSA_REF select PL011 # UART select PL031 # RTC select PL061 # GPIO - select USB_EHCI_SYSBUS + select USB_XHCI_SYSBUS select WDT_SBSA select BOCHS_DISPLAY diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 82a28b2e0b..c2e0a9fa1a 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -42,6 +42,7 @@ #include "hw/pci-host/gpex.h" #include "hw/qdev-properties.h" #include "hw/usb.h" +#include "hw/usb/xhci.h" #include "hw/char/pl011.h" #include "hw/watchdog/sbsa_gwdt.h" #include "net/net.h" @@ -85,7 +86,7 @@ enum { SBSA_SECURE_UART_MM, SBSA_SECURE_MEM, SBSA_AHCI, - SBSA_EHCI, + SBSA_XHCI, }; struct SBSAMachineState { @@ -123,7 +124,7 @@ static const MemMapEntry sbsa_ref_memmap[] = { [SBSA_SMMU] = { 0x60050000, 0x00020000 }, /* Space here reserved for more SMMUs */ [SBSA_AHCI] = { 0x60100000, 0x00010000 }, - [SBSA_EHCI] = { 0x60110000, 0x00010000 }, + [SBSA_XHCI] = { 0x60110000, 0x00010000 }, /* Space here reserved for other devices */ [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, /* 32-bit address PCIE MMIO space */ @@ -143,7 +144,7 @@ static const int sbsa_ref_irqmap[] = { [SBSA_SECURE_UART] = 8, [SBSA_SECURE_UART_MM] = 9, [SBSA_AHCI] = 10, - [SBSA_EHCI] = 11, + [SBSA_XHCI] = 11, [SBSA_SMMU] = 12, /* ... to 15 */ [SBSA_GWDT_WS0] = 16, }; @@ -152,6 +153,7 @@ static const char * const valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("neoverse-n1"), + ARM_CPU_TYPE_NAME("neoverse-v1"), ARM_CPU_TYPE_NAME("max"), }; @@ -230,7 +232,7 @@ static void create_fdt(SBSAMachineState *sms) * fw compatibility. */ qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); - qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 2); + qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3); if (ms->numa_state->have_numa_distance) { int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); @@ -604,13 +606,15 @@ static void create_ahci(const SBSAMachineState *sms) } } -static void create_ehci(const SBSAMachineState *sms) +static void create_xhci(const SBSAMachineState *sms) { - hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; - int irq = sbsa_ref_irqmap[SBSA_EHCI]; + hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; + int irq = sbsa_ref_irqmap[SBSA_XHCI]; + DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); - sysbus_create_simple("platform-ehci-usb", base, - qdev_get_gpio_in(sms->gic, irq)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); } static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) @@ -832,7 +836,7 @@ static void sbsa_ref_init(MachineState *machine) create_ahci(sms); - create_ehci(sms); + create_xhci(sms); create_pcie(sms); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3196db556e..796181e169 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -214,6 +214,7 @@ static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("a64fx"), ARM_CPU_TYPE_NAME("neoverse-n1"), + ARM_CPU_TYPE_NAME("neoverse-v1"), #endif ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), diff --git a/hw/misc/allwinner-sramc.c b/hw/misc/allwinner-sramc.c index a8b731f8f2..d76c24d081 100644 --- a/hw/misc/allwinner-sramc.c +++ b/hw/misc/allwinner-sramc.c @@ -159,6 +159,7 @@ static const TypeInfo allwinner_sramc_info = { .parent = TYPE_SYS_BUS_DEVICE, .instance_init = allwinner_sramc_init, .instance_size = sizeof(AwSRAMCState), + .class_size = sizeof(AwSRAMCClass), .class_init = allwinner_sramc_class_init, }; |