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authorPeter Maydell <peter.maydell@linaro.org>2017-06-06 17:00:12 +0100
committerPeter Maydell <peter.maydell@linaro.org>2017-06-06 17:00:12 +0100
commit65dfad62a176f5265f801683be64149c5ad55f7d (patch)
tree07aa5c610744a775d1ef6ed80ea869a7d4537450 /hw
parent572db7cd69bef46e94bd0bf6d7eacb1015ce714e (diff)
parentdd7b952b793e341c905355581a21cdbaa8b13c31 (diff)
Merge remote-tracking branch 'remotes/xtensa/tags/20170606-xtensa' into staging
target/xtensa fixes: - fix read/write simcall mapping flags and return value; - use -serial option to direct console output of sim machine to QEMU chardev; - fix handling of unknown registers in the gdbstub. # gpg: Signature made Tue 06 Jun 2017 11:46:05 BST # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20170606-xtensa: target/xtensa: handle unknown registers in gdbstub target/xtensa: support output to chardev console target/xtensa: fix return value of read/write simcalls target/xtensa: fix mapping direction in read/write simcalls Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/xtensa/sim.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c
index b27e28d802..5521e9184a 100644
--- a/hw/xtensa/sim.c
+++ b/hw/xtensa/sim.c
@@ -114,6 +114,9 @@ static void xtensa_sim_init(MachineState *machine)
xtensa_create_memory_regions(&sysram, "xtensa.sysram");
}
+ if (serial_hds[0]) {
+ xtensa_sim_open_console(serial_hds[0]);
+ }
if (kernel_filename) {
uint64_t elf_entry;
uint64_t elf_lowaddr;
@@ -136,6 +139,7 @@ static void xtensa_sim_machine_init(MachineClass *mc)
mc->is_default = true;
mc->init = xtensa_sim_init;
mc->max_cpus = 4;
+ mc->no_serial = 1;
}
DEFINE_MACHINE("sim", xtensa_sim_machine_init)