diff options
| author | Cédric Le Goater <clg@kaod.org> | 2019-11-25 07:58:06 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-12-17 10:39:47 +1100 |
| commit | 5014c60261cf38b7c210831548c042982218a999 (patch) | |
| tree | 16a7a9dd3de1b77f32015b9bd010d1c284e3b535 /hw | |
| parent | 4a89e20458ef6ef0979d9a05e41b421fe28a90a8 (diff) | |
ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper
and use this helper to exclude CPUs which are not enabled in the XIVE
controller.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-7-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/intc/pnv_xive.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 9798bd9e72..ec8349ee4a 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -372,6 +372,21 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx, return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas); } +/* + * One bit per thread id. The first register PC_THREAD_EN_REG0 covers + * the first cores 0-15 (normal) of the chip or 0-7 (fused). The + * second register covers cores 16-23 (normal) or 8-11 (fused). + */ +static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu) +{ + int pir = ppc_cpu_pir(cpu); + uint32_t fc = PNV9_PIR2FUSEDCORE(pir); + uint64_t reg = fc < 8 ? PC_THREAD_EN_REG0 : PC_THREAD_EN_REG1; + uint32_t bit = pir & 0x3f; + + return xive->regs[reg >> 3] & PPC_BIT(bit); +} + static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, @@ -391,6 +406,10 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, XiveTCTX *tctx; int ring; + if (!pnv_xive_is_cpu_enabled(xive, cpu)) { + continue; + } + tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); /* |