diff options
author | Cédric Le Goater <clg@kaod.org> | 2018-12-11 23:38:16 +0100 |
---|---|---|
committer | David Gibson <david@gibson.dropbear.id.au> | 2018-12-21 09:39:13 +1100 |
commit | 1c53b06c0309104f30ca2c5e1d1e89ddc38de080 (patch) | |
tree | 52f638547ccfffe79e2610867d5a27cafe8f123e /hw | |
parent | 1a937ad7e7a1b4eef37c967cbaeeda5ec5b90855 (diff) |
spapr: extend the sPAPR IRQ backend for XICS migration
Introduce a new sPAPR IRQ handler to handle resend after migration
when the machine is using a KVM XICS interrupt controller model.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/ppc/spapr.c | 13 | ||||
-rw-r--r-- | hw/ppc/spapr_irq.c | 27 |
2 files changed, 32 insertions, 8 deletions
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index dfb617e580..0b09a88753 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1730,14 +1730,6 @@ static int spapr_post_load(void *opaque, int version_id) return err; } - if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { - CPUState *cs; - CPU_FOREACH(cs) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - icp_resend(ICP(cpu->intc)); - } - } - /* In earlier versions, there was no separate qdev for the PAPR * RTC, so the RTC offset was stored directly in sPAPREnvironment. * So when migrating from those versions, poke the incoming offset @@ -1758,6 +1750,11 @@ static int spapr_post_load(void *opaque, int version_id) } } + err = spapr_irq_post_load(spapr, version_id); + if (err) { + return err; + } + return err; } diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index fdcc7795e4..292c448a15 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -197,6 +197,18 @@ static Object *spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr, return icp_create(cpu, spapr->icp_type, XICS_FABRIC(spapr), errp); } +static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id) +{ + if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { + CPUState *cs; + CPU_FOREACH(cs) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + icp_resend(ICP(cpu->intc)); + } + } + return 0; +} + #define SPAPR_IRQ_XICS_NR_IRQS 0x1000 #define SPAPR_IRQ_XICS_NR_MSIS \ (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI) @@ -212,6 +224,7 @@ sPAPRIrq spapr_irq_xics = { .print_info = spapr_irq_print_info_xics, .dt_populate = spapr_dt_xics, .cpu_intc_create = spapr_irq_cpu_intc_create_xics, + .post_load = spapr_irq_post_load_xics, }; /* @@ -295,6 +308,11 @@ static Object *spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr, return xive_tctx_create(cpu, XIVE_ROUTER(spapr->xive), errp); } +static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id) +{ + return 0; +} + /* * XIVE uses the full IRQ number space. Set it to 8K to be compatible * with XICS. @@ -314,6 +332,7 @@ sPAPRIrq spapr_irq_xive = { .print_info = spapr_irq_print_info_xive, .dt_populate = spapr_dt_xive, .cpu_intc_create = spapr_irq_cpu_intc_create_xive, + .post_load = spapr_irq_post_load_xive, }; /* @@ -352,6 +371,13 @@ qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq) return smc->irq->qirq(spapr, irq); } +int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id) +{ + sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); + + return smc->irq->post_load(spapr, version_id); +} + /* * XICS legacy routines - to deprecate one day */ @@ -420,4 +446,5 @@ sPAPRIrq spapr_irq_xics_legacy = { .print_info = spapr_irq_print_info_xics, .dt_populate = spapr_dt_xics, .cpu_intc_create = spapr_irq_cpu_intc_create_xics, + .post_load = spapr_irq_post_load_xics, }; |