aboutsummaryrefslogtreecommitdiff
path: root/hw
diff options
context:
space:
mode:
authorPeter Maydell <peter.maydell@linaro.org>2017-03-07 09:57:14 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-03-07 09:57:14 +0000
commitff79d5e939c38677a575e3493eb9b4d36eb21865 (patch)
tree3b9d82d69fea48dca95fee5fdff2b6379b7eab29 /hw
parentd6780c822144f6b0ae81dd2793dfe84179294822 (diff)
parentcb3825b9afdb1800cef1be9c9a732c803d8bb29e (diff)
Merge remote-tracking branch 'remotes/xtensa/tags/20170306-xtensa' into staging
target/xtensa updates: - instantiate local memories in xtensa sim machine; - add two missing include files to xtensa core importing script. # gpg: Signature made Mon 06 Mar 2017 22:32:45 GMT # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20170306-xtensa: target/xtensa: add two missing headers to core import script target/xtensa: sim: instantiate local memories Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/xtensa/sim.c40
1 files changed, 31 insertions, 9 deletions
diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c
index 5e94004261..d2d1d3a6fd 100644
--- a/hw/xtensa/sim.c
+++ b/hw/xtensa/sim.c
@@ -37,6 +37,27 @@
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
+static void xtensa_create_memory_regions(const XtensaMemory *memory,
+ const char *name)
+{
+ unsigned i;
+ char *num_name = malloc(strlen(name) + sizeof(i) * 3 + 1);
+
+ for (i = 0; i < memory->num; ++i) {
+ MemoryRegion *m;
+
+ sprintf(num_name, "%s%u", name, i);
+ m = g_malloc(sizeof(*m));
+ memory_region_init_ram(m, NULL, num_name,
+ memory->location[i].size,
+ &error_fatal);
+ vmstate_register_ram_global(m);
+ memory_region_add_subregion(get_system_memory(),
+ memory->location[i].addr, m);
+ }
+ free(num_name);
+}
+
static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
{
XtensaCPU *cpu = opaque;
@@ -55,7 +76,6 @@ static void xtensa_sim_init(MachineState *machine)
{
XtensaCPU *cpu = NULL;
CPUXtensaState *env = NULL;
- MemoryRegion *ram, *rom;
ram_addr_t ram_size = machine->ram_size;
const char *cpu_model = machine->cpu_model;
const char *kernel_filename = machine->kernel_filename;
@@ -82,15 +102,17 @@ static void xtensa_sim_init(MachineState *machine)
sim_reset(cpu);
}
- ram = g_malloc(sizeof(*ram));
- memory_region_init_ram(ram, NULL, "xtensa.sram", ram_size, &error_fatal);
- vmstate_register_ram_global(ram);
- memory_region_add_subregion(get_system_memory(), 0, ram);
+ if (env) {
+ XtensaMemory sysram = env->config->sysram;
- rom = g_malloc(sizeof(*rom));
- memory_region_init_ram(rom, NULL, "xtensa.rom", 0x1000, &error_fatal);
- vmstate_register_ram_global(rom);
- memory_region_add_subregion(get_system_memory(), 0xfe000000, rom);
+ sysram.location[0].size = ram_size;
+ xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom");
+ xtensa_create_memory_regions(&env->config->instram, "xtensa.instram");
+ xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom");
+ xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram");
+ xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom");
+ xtensa_create_memory_regions(&sysram, "xtensa.sysram");
+ }
if (kernel_filename) {
uint64_t elf_entry;