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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2020-03-05 16:09:13 +0000
committerPeter Maydell <peter.maydell@linaro.org>2020-03-05 16:09:13 +0000
commit8a21865157b4d234f0ea1a5862feb913813e9409 (patch)
treed8a7d535a52907da96a059d29f5e1d76ec85554f /hw
parente64a62df378a746c0b257105959613c9f8122e59 (diff)
hw/arm: versal: Add support for the LPD ADMAs
Add support for the Versal LPD ADMAs. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/arm/xlnx-versal.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 403fc7b881..cb0122a3a6 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -194,6 +194,29 @@ static void versal_create_gems(Versal *s, qemu_irq *pic)
}
}
+static void versal_create_admas(Versal *s, qemu_irq *pic)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
+ char *name = g_strdup_printf("adma%d", i);
+ DeviceState *dev;
+ MemoryRegion *mr;
+
+ dev = qdev_create(NULL, "xlnx.zdma");
+ s->lpd.iou.adma[i] = SYS_BUS_DEVICE(dev);
+ object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
+ qdev_init_nofail(dev);
+
+ mr = sysbus_mmio_get_region(s->lpd.iou.adma[i], 0);
+ memory_region_add_subregion(&s->mr_ps,
+ MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr);
+
+ sysbus_connect_irq(s->lpd.iou.adma[i], 0, pic[VERSAL_ADMA_IRQ_0 + i]);
+ g_free(name);
+ }
+}
+
/* This takes the board allocated linear DDR memory and creates aliases
* for each split DDR range/aperture on the Versal address map.
*/
@@ -275,6 +298,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
versal_create_apu_gic(s, pic);
versal_create_uarts(s, pic);
versal_create_gems(s, pic);
+ versal_create_admas(s, pic);
versal_map_ddr(s);
versal_unimp(s);