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authorPeter Crosthwaite <peter.crosthwaite@xilinx.com>2013-04-03 14:52:21 +1000
committerPeter Maydell <peter.maydell@linaro.org>2013-04-05 17:03:01 +0100
commit1db8b5efe0c2b5000e50691eea61264a615f43de (patch)
treedba62b8901afbe8ffb2bf88abe641fc6038feab3 /hw
parentfd7f8a99f3b08640a7fe2b2f3c3e6b68068b4983 (diff)
cadence_uart: Flush queued characters on reset
Reset can be used to empty the rx-fifo. As the fifo full condition is used to return false from can_receive, queued rx data should be flushed on reset accordingly. Cc: Wendy Liang <jliang@xilinx.com> Cc: Jason Wu <huanyu@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reported-by: Jason Wu <huanyu@xilinx.com> Message-id: 494c1e005e225c915d295ddfd75d992ad2dabc3c.1364964526.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/cadence_uart.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c
index 5426f10018..421ec998d6 100644
--- a/hw/cadence_uart.c
+++ b/hw/cadence_uart.c
@@ -157,6 +157,7 @@ static void uart_rx_reset(UartState *s)
{
s->rx_wpos = 0;
s->rx_count = 0;
+ qemu_chr_accept_input(s->chr);
s->r[R_SR] |= UART_SR_INTR_REMPTY;
s->r[R_SR] &= ~UART_SR_INTR_RFUL;