diff options
| author | Cédric Le Goater <clg@kaod.org> | 2017-09-08 16:33:42 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-09-15 10:29:48 +1000 |
| commit | 21f3f8db0e61884ca48e9969b0305d54f1efe24b (patch) | |
| tree | 61ab79f0c997c318f802f004e6fd4bf6bfdf1b80 /hw | |
| parent | 4c563d9df556454e6278035927e9e082a05b30af (diff) | |
ppc/xive: fix OV5_XIVE_EXPLOIT bits
On POWER9, the Client Architecture Support (CAS) negotiation process
determines whether the guest operates in XIVE Legacy compatibility or
in XIVE exploitation mode. Now that we have initial guest support for
the XIVE interrupt controller, let's fix the bits definition which have
evolved in the latest specs.
The platform advertises the XIVE Exploitation Mode support using the
property "ibm,arch-vec-5-platform-support-vec-5", byte 23 bits 0-1 :
- 0b00 XIVE legacy mode Only
- 0b01 XIVE exploitation mode Only
- 0b10 XIVE legacy or exploitation mode
The OS asks for XIVE Exploitation Mode support using the property
"ibm,architecture-vec-5", byte 23 bits 0-1:
- 0b00 XIVE legacy mode Only
- 0b01 XIVE exploitation mode Only
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/ppc/spapr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 06a008b43c..f680f28a15 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -937,7 +937,7 @@ static void spapr_dt_ov5_platform_support(void *fdt, int chosen) PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); char val[2 * 4] = { - 23, 0x00, /* Xive mode: 0 = legacy (as in ISA 2.7), 1 = Exploitation */ + 23, 0x00, /* Xive mode, filled in below. */ 24, 0x00, /* Hash/Radix, filled in below. */ 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 26, 0x40, /* Radix options: GTSE == yes. */ |