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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2020-05-06 10:25:05 +0200
committerEdgar E. Iglesias <edgar.iglesias@xilinx.com>2020-05-14 13:44:35 +0200
commit3e2a0cb99d26fd5fb34ab8c50f90d4292363245d (patch)
tree4f2ddfd46849f8a4747a85b08f5f78c3238556f0 /hw
parent035b448b84f3557206abc44d786c5d3db2638f7d (diff)
hw/net/xilinx_axienet: Auto-clear PHY Autoneg
Auto-clear PHY CR Autoneg bits. This makes this model work with recent Linux kernels. Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <20200506082513.18751-2-edgar.iglesias@gmail.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/net/xilinx_axienet.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index 704788811a..0f97510d8a 100644
--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
@@ -149,8 +149,8 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
break;
}
- /* Unconditionally clear regs[BMCR][BMCR_RESET] */
- phy->regs[0] &= ~0x8000;
+ /* Unconditionally clear regs[BMCR][BMCR_RESET] and auto-neg */
+ phy->regs[0] &= ~0x8200;
}
static void