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authorAurelien Jarno <aurelien@aurel32.net>2015-07-15 17:05:09 +0200
committerLeon Alrae <leon.alrae@imgtec.com>2015-08-13 16:22:52 +0100
commiteb02cc3f89013612cb05df23b5441741e902bbd2 (patch)
tree3c520356c13e7cc307cb77db087d1bc795fb8b5a /hw
parentaff2bc6dc6d839caf6df0900437cc2cc9e180605 (diff)
target-mips: simplify LWL/LDL mask generation
The LWL/LDL instructions mask the GPR with a mask depending on the address alignement. It is currently computed by doing: mask = 0x7fffffffffffffffull >> (t1 ^ 63) It's simpler to generate it by doing: mask = ~(-1 << t1) It uses one TCG instruction less, and it avoids a 32/64-bit constant loading which can take a few instructions on RISC hosts. Cc: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'hw')
0 files changed, 0 insertions, 0 deletions