diff options
| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-01-16 21:38:58 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-01-16 21:38:58 +0000 |
| commit | 35730fa05511cfbf19341aedf8bfd526dfc7d90f (patch) | |
| tree | 76e18f36aba091be78394a7e6adada7c6c708937 /hw | |
| parent | 0add30cff44d681d0490b167e666c39d4d7b1e8d (diff) | |
hpet config mask fix
I discovered a bug in the hpet code that caused Windows to boot without
hpet. The config mask I was using was preventing the guest from placing
the hpet into 32 bit mode.
(Beth Kon)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6357 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/hpet.c | 6 | ||||
| -rw-r--r-- | hw/hpet_emul.h | 2 |
2 files changed, 6 insertions, 2 deletions
@@ -388,7 +388,8 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr, switch ((addr - 0x100) % 0x20) { case HPET_TN_CFG: dprintf("qemu: hpet_ram_writel HPET_TN_CFG\n"); - timer->config = hpet_fixup_reg(new_val, old_val, 0x3e4e); + timer->config = hpet_fixup_reg(new_val, old_val, + HPET_TN_CFG_WRITE_MASK); if (new_val & HPET_TN_32BIT) { timer->cmp = (uint32_t)timer->cmp; timer->period = (uint32_t)timer->period; @@ -456,7 +457,8 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr, case HPET_ID: return; case HPET_CFG: - s->config = hpet_fixup_reg(new_val, old_val, 0x3); + s->config = hpet_fixup_reg(new_val, old_val, + HPET_CFG_WRITE_MASK); if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) { /* Enable main counter and interrupt generation. */ s->hpet_offset = ticks_to_ns(s->hpet_counter) diff --git a/hw/hpet_emul.h b/hw/hpet_emul.h index fbe7a44531..60893b65d0 100644 --- a/hw/hpet_emul.h +++ b/hw/hpet_emul.h @@ -36,6 +36,7 @@ #define HPET_TN_CFG 0x000 #define HPET_TN_CMP 0x008 #define HPET_TN_ROUTE 0x010 +#define HPET_CFG_WRITE_MASK 0x3 #define HPET_TN_ENABLE 0x004 @@ -45,6 +46,7 @@ #define HPET_TN_SETVAL 0x040 #define HPET_TN_32BIT 0x100 #define HPET_TN_INT_ROUTE_MASK 0x3e00 +#define HPET_TN_CFG_WRITE_MASK 0x3f4e #define HPET_TN_INT_ROUTE_SHIFT 9 #define HPET_TN_INT_ROUTE_CAP_SHIFT 32 #define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U |