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authorPeter Crosthwaite <peter.crosthwaite@xilinx.com>2014-01-06 10:16:40 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-01-08 19:07:21 +0000
commit86baecc3e43510c3bef03a0d7e947221823864d3 (patch)
tree4dc84b492c3a1502f63fae443b5d7b4bbae1e3cd /hw
parentd0ac820fe4152ea3a57fc3fa9f732cc9524017a4 (diff)
char/cadence_uart: Use the TX fifo for transmission
Populate the TxFIFO with the Tx data before sending. Prepares support for proper Tx flow control implementation. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: bdf7f8af2ef02839bea18665701bc2612f7baa6f.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/char/cadence_uart.c17
1 files changed, 16 insertions, 1 deletions
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index 3bcaf2905d..be32126bdc 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -292,7 +292,22 @@ static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size)
return;
}
- qemu_chr_fe_write_all(s->chr, buf, size);
+ if (size > TX_FIFO_SIZE - s->tx_count) {
+ size = TX_FIFO_SIZE - s->tx_count;
+ /*
+ * This can only be a guest error via a bad tx fifo register push,
+ * as can_receive() should stop remote loop and echo modes ever getting
+ * us to here.
+ */
+ qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow");
+ s->r[R_CISR] |= UART_INTR_ROVR;
+ }
+
+ memcpy(s->tx_fifo + s->tx_count, buf, size);
+ s->tx_count += size;
+
+ qemu_chr_fe_write_all(s->chr, s->tx_fifo, s->tx_count);
+ s->tx_count = 0;
}
static void uart_receive(void *opaque, const uint8_t *buf, int size)