More PowerPC debug print fixes - hardware emulation pass.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3726 c046a42c-6fe2-441c-8c8c-71466251a162

6 files changed, 134 insertions, 117 deletions

diff --git a/hw/ppc.c b/hw/ppc.c
index 9145101540..fc92ab2673 100644
--- a/hw/ppc.c
+++ b/hw/ppc.c
@@ -48,8 +48,8 @@ static void ppc_set_irq (CPUState *env, int n_IRQ, int level)
     }
 #if defined(PPC_DEBUG_IRQ)
     if (loglevel & CPU_LOG_INT) {
-        fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08x req %08x\n",
-                __func__, env, n_IRQ, level,
+        fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08" PRIx32
+                "req %08x\n", __func__, env, n_IRQ, level,
                 env->pending_interrupts, env->interrupt_request);
     }
 #endif
@@ -457,7 +457,7 @@ uint32_t cpu_ppc_load_tbl (CPUState *env)
     tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
 #if defined(PPC_DEBUG_TB)
     if (loglevel != 0) {
-        fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
+        fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);
     }
 #endif
 
@@ -472,7 +472,7 @@ static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env)
     tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
 #if defined(PPC_DEBUG_TB)
     if (loglevel != 0) {
-        fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
+        fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);
     }
 #endif
 
@@ -491,8 +491,8 @@ static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t vmclk,
     *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec);
 #ifdef PPC_DEBUG_TB
     if (loglevel != 0) {
-        fprintf(logfile, "%s: tb=0x%016lx offset=%08lx\n", __func__, value,
-                *tb_offsetp);
+        fprintf(logfile, "%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",
+                __func__, value, *tb_offsetp);
     }
 #endif
 }
@@ -532,7 +532,7 @@ uint32_t cpu_ppc_load_atbl (CPUState *env)
     tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
 #if defined(PPC_DEBUG_TB)
     if (loglevel != 0) {
-        fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
+        fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);
     }
 #endif
 
@@ -547,7 +547,7 @@ uint32_t cpu_ppc_load_atbu (CPUState *env)
     tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
 #if defined(PPC_DEBUG_TB)
     if (loglevel != 0) {
-        fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
+        fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);
     }
 #endif
 
@@ -602,7 +602,7 @@ static void cpu_ppc_tb_start (CPUState *env)
 {
     ppc_tb_t *tb_env = env->tb_env;
     uint64_t tb, atb, vmclk;
-    
+
     /* If the time base is not frozen, do nothing */
     if (tb_env->tb_freq == 0) {
         vmclk = qemu_get_clock(vm_clock);
@@ -633,7 +633,7 @@ static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env,
         decr = -muldiv64(-diff, tb_env->decr_freq, ticks_per_sec);
 #if defined(PPC_DEBUG_TB)
     if (loglevel != 0) {
-        fprintf(logfile, "%s: 0x%08x\n", __func__, decr);
+        fprintf(logfile, "%s: %08" PRIx32 "\n", __func__, decr);
     }
 #endif
 
@@ -700,7 +700,8 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
 
 #ifdef PPC_DEBUG_TB
     if (loglevel != 0) {
-        fprintf(logfile, "%s: 0x%08x => 0x%08x\n", __func__, decr, value);
+        fprintf(logfile, "%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
+                decr, value);
     }
 #endif
     now = qemu_get_clock(vm_clock);
@@ -910,7 +911,7 @@ static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
     } else {
 #ifdef PPC_DEBUG_TB
         if (loglevel != 0) {
-            fprintf(logfile, "%s: start PIT 0x" REGX "\n",
+            fprintf(logfile, "%s: start PIT %016" PRIx64 "\n",
                     __func__, ppcemb_timer->pit_reload);
         }
 #endif
@@ -1032,7 +1033,7 @@ void store_40x_pit (CPUState *env, target_ulong val)
     ppcemb_timer = tb_env->opaque;
 #ifdef PPC_DEBUG_TB
     if (loglevel != 0) {
-        fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
+        fprintf(logfile, "%s val" ADDRX "\n", __func__, val);
     }
 #endif
     ppcemb_timer->pit_reload = val;
@@ -1048,7 +1049,7 @@ void store_booke_tsr (CPUState *env, target_ulong val)
 {
 #ifdef PPC_DEBUG_TB
     if (loglevel != 0) {
-        fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
+        fprintf(logfile, "%s: val " ADDRX "\n", __func__, val);
     }
 #endif
     env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
@@ -1063,7 +1064,7 @@ void store_booke_tcr (CPUState *env, target_ulong val)
     tb_env = env->tb_env;
 #ifdef PPC_DEBUG_TB
     if (loglevel != 0) {
-        fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
+        fprintf(logfile, "%s: val " ADDRX "\n", __func__, val);
     }
 #endif
     env->spr[SPR_40x_TCR] = val & 0xFFC00000;
@@ -1078,7 +1079,8 @@ static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq)
 
 #ifdef PPC_DEBUG_TB
     if (loglevel != 0) {
-        fprintf(logfile, "%s set new frequency to %u\n", __func__, freq);
+        fprintf(logfile, "%s set new frequency to %" PRIu32 "\n", __func__,
+                freq);
     }
 #endif
     tb_env->tb_freq = freq;
@@ -1102,8 +1104,7 @@ clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq)
     tb_env->opaque = ppcemb_timer;
 #ifdef PPC_DEBUG_TB
     if (loglevel != 0) {
-        fprintf(logfile, "%s %p %p %p\n", __func__, tb_env, ppcemb_timer,
-                &ppc_emb_set_tb_clk);
+        fprintf(logfile, "%s freq %" PRIu32 "\n", __func__, freq);
     }
 #endif
     if (ppcemb_timer != NULL) {
@@ -1239,7 +1240,7 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
         fflush(stdout);
         break;
     case 2:
-        printf("Set loglevel to %04x\n", val);
+        printf("Set loglevel to %04" PRIx32 "\n", val);
         cpu_set_log(val | 0x100);
         break;
     }
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index 0a2f087d85..329330a61c 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -40,7 +40,7 @@ extern FILE *logfile;
 #define DEBUG_GPT
 #define DEBUG_MAL
 #define DEBUG_CLOCKS
-//#define DEBUG_UNASSIGNED
+//#define DEBUG_CLOCKS_LL
 
 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
                                 uint32_t flags)
@@ -298,7 +298,7 @@ static void opba_writeb (void *opaque,
     ppc4xx_opba_t *opba;
 
 #ifdef DEBUG_OPBA
-    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
+    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 #endif
     opba = opaque;
     switch (addr - opba->base) {
@@ -330,7 +330,7 @@ static void opba_writew (void *opaque,
                          target_phys_addr_t addr, uint32_t value)
 {
 #ifdef DEBUG_OPBA
-    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
+    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 #endif
     opba_writeb(opaque, addr, value >> 8);
     opba_writeb(opaque, addr + 1, value);
@@ -353,7 +353,7 @@ static void opba_writel (void *opaque,
                          target_phys_addr_t addr, uint32_t value)
 {
 #ifdef DEBUG_OPBA
-    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
+    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 #endif
     opba_writeb(opaque, addr, value >> 24);
     opba_writeb(opaque, addr + 1, value >> 16);
@@ -389,7 +389,7 @@ void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
     if (opba != NULL) {
         opba->base = offset;
 #ifdef DEBUG_OPBA
-        printf("%s: offset=" PADDRX "\n", __func__, offset);
+        printf("%s: offset " PADDRX "\n", __func__, offset);
 #endif
         ppc4xx_mmio_register(env, mmio, offset, 0x002,
                              opba_read, opba_write, opba);
@@ -429,6 +429,10 @@ enum {
     SDRAM0_CFGDATA = 0x011,
 };
 
+/* XXX: TOFIX: some patches have made this code become inconsistent:
+ *      there are type inconsistencies, mixing target_phys_addr_t, target_ulong
+ *      and uint32_t
+ */
 static uint32_t sdram_bcr (target_phys_addr_t ram_base,
                            target_phys_addr_t ram_size)
 {
@@ -457,8 +461,7 @@ static uint32_t sdram_bcr (target_phys_addr_t ram_base,
         bcr = 0x000C0000;
         break;
     default:
-        printf("%s: invalid RAM size " TARGET_FMT_plx "\n",
-               __func__, ram_size);
+        printf("%s: invalid RAM size " PADDRX "\n", __func__, ram_size);
         return 0x00000000;
     }
     bcr |= ram_base & 0xFF800000;
@@ -491,7 +494,7 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
     if (*bcrp & 0x00000001) {
         /* Unmap RAM */
 #ifdef DEBUG_SDRAM
-        printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
+        printf("%s: unmap RAM area " PADDRX " " ADDRX "\n",
                __func__, sdram_base(*bcrp), sdram_size(*bcrp));
 #endif
         cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
@@ -500,7 +503,7 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
     *bcrp = bcr & 0xFFDEE001;
     if (enabled && (bcr & 0x00000001)) {
 #ifdef DEBUG_SDRAM
-        printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
+        printf("%s: Map RAM area " PADDRX " " ADDRX "\n",
                __func__, sdram_base(bcr), sdram_size(bcr));
 #endif
         cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
@@ -529,7 +532,7 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
 
     for (i = 0; i < sdram->nbanks; i++) {
 #ifdef DEBUG_SDRAM
-        printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
+        printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n",
                __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
 #endif
         cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
@@ -1110,7 +1113,7 @@ static void ppc405_gpio_writeb (void *opaque,
 
     gpio = opaque;
 #ifdef DEBUG_GPIO
-    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
+    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 #endif
 }
 
@@ -1133,7 +1136,7 @@ static void ppc405_gpio_writew (void *opaque,
 
     gpio = opaque;
 #ifdef DEBUG_GPIO
-    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
+    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 #endif
 }
 
@@ -1156,7 +1159,7 @@ static void ppc405_gpio_writel (void *opaque,
 
     gpio = opaque;
 #ifdef DEBUG_GPIO
-    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
+    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 #endif
 }
 
@@ -1190,7 +1193,7 @@ void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
         ppc405_gpio_reset(gpio);
         qemu_register_reset(&ppc405_gpio_reset, gpio);
 #ifdef DEBUG_GPIO
-        printf("%s: offset=" PADDRX "\n", __func__, offset);
+        printf("%s: offset " PADDRX "\n", __func__, offset);
 #endif
         ppc4xx_mmio_register(env, mmio, offset, 0x038,
                              ppc405_gpio_read, ppc405_gpio_write, gpio);
@@ -1218,7 +1221,7 @@ void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
     void *serial;
 
 #ifdef DEBUG_SERIAL
-    printf("%s: offset=" PADDRX "\n", __func__, offset);
+    printf("%s: offset " PADDRX "\n", __func__, offset);
 #endif
     serial = serial_mm_init(offset, 0, irq, chr, 0);
     ppc4xx_mmio_register(env, mmio, offset, 0x008,
@@ -1248,7 +1251,9 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
                                  uint32_t dsarc, uint32_t dsacntl)
 {
 #ifdef DEBUG_OCM
-    printf("OCM update ISA %08x %08x (%08x %08x) DSA %08x %08x (%08x %08x)\n",
+    printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
+           " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
+           " (%08" PRIx32 " %08" PRIx32 ")\n",
            isarc, isacntl, dsarc, dsacntl,
            ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
 #endif
@@ -1256,14 +1261,14 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
         (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
         if (ocm->isacntl & 0x80000000) {
             /* Unmap previously assigned memory region */
-            printf("OCM unmap ISA %08x\n", ocm->isarc);
+            printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
             cpu_register_physical_memory(ocm->isarc, 0x04000000,
                                          IO_MEM_UNASSIGNED);
         }
         if (isacntl & 0x80000000) {
             /* Map new instruction memory region */
 #ifdef DEBUG_OCM
-            printf("OCM map ISA %08x\n", isarc);
+            printf("OCM map ISA %08" PRIx32 "\n", isarc);
 #endif
             cpu_register_physical_memory(isarc, 0x04000000,
                                          ocm->offset | IO_MEM_RAM);
@@ -1276,7 +1281,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
             if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
                 /* Unmap previously assigned memory region */
 #ifdef DEBUG_OCM
-                printf("OCM unmap DSA %08x\n", ocm->dsarc);
+                printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
 #endif
                 cpu_register_physical_memory(ocm->dsarc, 0x04000000,
                                              IO_MEM_UNASSIGNED);
@@ -1287,7 +1292,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
             if (!(isacntl & 0x80000000) || dsarc != isarc) {
                 /* Map new data memory region */
 #ifdef DEBUG_OCM
-                printf("OCM map DSA %08x\n", dsarc);
+                printf("OCM map DSA %08" PRIx32 "\n", dsarc);
 #endif
                 cpu_register_physical_memory(dsarc, 0x04000000,
                                              ocm->offset | IO_MEM_RAM);
@@ -1475,7 +1480,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
         break;
     }
 #ifdef DEBUG_I2C
-    printf("%s: addr " PADDRX " %02x\n", __func__, addr, ret);
+    printf("%s: addr " PADDRX " %02" PRIx32 "\n", __func__, addr, ret);
 #endif
 
     return ret;
@@ -1487,7 +1492,7 @@ static void ppc4xx_i2c_writeb (void *opaque,
     ppc4xx_i2c_t *i2c;
 
 #ifdef DEBUG_I2C
-    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
+    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 #endif
     i2c = opaque;
     switch (addr - i2c->base) {
@@ -1557,7 +1562,7 @@ static void ppc4xx_i2c_writew (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
 {
 #ifdef DEBUG_I2C
-    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
+    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 #endif
     ppc4xx_i2c_writeb(opaque, addr, value >> 8);
     ppc4xx_i2c_writeb(opaque, addr + 1, value);
@@ -1582,7 +1587,7 @@ static void ppc4xx_i2c_writel (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
 {
 #ifdef DEBUG_I2C
-    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
+    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 #endif
     ppc4xx_i2c_writeb(opaque, addr, value >> 24);
     ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
@@ -1629,7 +1634,7 @@ void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
         i2c->irq = irq;
         ppc4xx_i2c_reset(i2c);
 #ifdef DEBUG_I2C
-        printf("%s: offset=" PADDRX "\n", __func__, offset);
+        printf("%s: offset " PADDRX "\n", __func__, offset);
 #endif
         ppc4xx_mmio_register(env, mmio, offset, 0x011,
                              i2c_read, i2c_write, i2c);
@@ -1668,7 +1673,7 @@ static void ppc4xx_gpt_writeb (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
 {
 #ifdef DEBUG_I2C
-    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
+    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 #endif
     /* XXX: generate a bus fault */
 }
@@ -1686,7 +1691,7 @@ static void ppc4xx_gpt_writew (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
 {
 #ifdef DEBUG_I2C
-    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
+    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 #endif
     /* XXX: generate a bus fault */
 }
@@ -1805,7 +1810,7 @@ static void ppc4xx_gpt_writel (void *opaque,
     int idx;
 
 #ifdef DEBUG_I2C
-    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
+    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 #endif
     gpt = opaque;
     switch (addr - gpt->base) {
@@ -1913,7 +1918,7 @@ void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
         gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
         ppc4xx_gpt_reset(gpt);
 #ifdef DEBUG_GPT
-        printf("%s: offset=" PADDRX "\n", __func__, offset);
+        printf("%s: offset " PADDRX "\n", __func__, offset);
 #endif
         ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
                              gpt_read, gpt_write, gpt);
@@ -2656,9 +2661,13 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
     VCO_out = 0;
     if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
         M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
-        //        printf("FBMUL %01x %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
+#ifdef DEBUG_CLOCKS_LL
+        printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
+#endif
         D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
-        //        printf("FWDA %01x %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
+#ifdef DEBUG_CLOCKS_LL
+        printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
+#endif
         VCO_out = cpc->sysclk * M * D;
         if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
             /* Error - unlock the PLL */
@@ -2683,53 +2692,53 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
     }
     /* Now, compute all other clocks */
     D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
-#ifdef DEBUG_CLOCKS
-    //    printf("CCDV %01x %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
+#ifdef DEBUG_CLOCKS_LL
+    printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
 #endif
     CPU_clk = PLL_out / D;
     D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
-#ifdef DEBUG_CLOCKS
-    //    printf("CBDV %01x %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
+#ifdef DEBUG_CLOCKS_LL
+    printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
 #endif
     PLB_clk = CPU_clk / D;
     D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
-#ifdef DEBUG_CLOCKS
-    //    printf("OPDV %01x %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
+#ifdef DEBUG_CLOCKS_LL
+    printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
 #endif
     OPB_clk = PLB_clk / D;
     D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
-#ifdef DEBUG_CLOCKS
-    //    printf("EPDV %01x %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
+#ifdef DEBUG_CLOCKS_LL
+    printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
 #endif
     EBC_clk = PLB_clk / D;
     D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
-#ifdef DEBUG_CLOCKS
-    //    printf("MPDV %01x %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
+#ifdef DEBUG_CLOCKS_LL
+    printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
 #endif
     MAL_clk = PLB_clk / D;
     D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
-#ifdef DEBUG_CLOCKS
-    //    printf("PPDV %01x %d\n", cpc->pllmr[0] & 0x3, D);
+#ifdef DEBUG_CLOCKS_LL
+    printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
 #endif
     PCI_clk = PLB_clk / D;
     D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
-#ifdef DEBUG_CLOCKS
-    //    printf("U0DIV %01x %d\n", cpc->ucr & 0x7F, D);
+#ifdef DEBUG_CLOCKS_LL
+    printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
 #endif
     UART0_clk = PLL_out / D;
     D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
-#ifdef DEBUG_CLOCKS
-    //    printf("U1DIV %01x %d\n", (cpc->ucr >> 8) & 0x7F, D);
+#ifdef DEBUG_CLOCKS_LL
+    printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
 #endif
     UART1_clk = PLL_out / D;
 #ifdef DEBUG_CLOCKS
-    printf("Setup PPC405EP clocks - sysclk %d VCO %" PRIu64
+    printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
            " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
-    printf("CPU %d PLB %d OPB %d EBC %d MAL %d PCI %d UART0 %d UART1 %d\n",
+    printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
+           " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
+           " UART1 %" PRIu32 "\n",
            CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
            UART0_clk, UART1_clk);
-    printf("CB %p opaque %p\n", cpc->clk_setup[PPC405EP_CPU_CLK].cb,
-           cpc->clk_setup[PPC405EP_CPU_CLK].opaque);
 #endif
     /* Setup CPU clocks */
     clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c
index be71879299..c4da27f4aa 100644
--- a/hw/ppc4xx_devs.c
+++ b/hw/ppc4xx_devs.c
@@ -30,6 +30,7 @@ extern int loglevel;
 extern FILE *logfile;
 
 //#define DEBUG_MMIO
+//#define DEBUG_UNASSIGNED
 #define DEBUG_UIC
 
 /*****************************************************************************/
@@ -136,8 +137,8 @@ static void mmio_writelen (ppc4xx_mmio_t *mmio,
 
     idx = MMIO_IDX(addr - mmio->base);
 #if defined(DEBUG_MMIO)
-    printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08x\n", __func__,
-           mmio, len, addr, idx, value);
+    printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08" PRIx32 "\n",
+           __func__, mmio, len, addr, idx, value);
 #endif
     mem_write = mmio->mem_write[idx];
     (*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value);
@@ -156,7 +157,7 @@ static void mmio_writeb (void *opaque,
                          target_phys_addr_t addr, uint32_t value)
 {
 #if defined(DEBUG_MMIO)
-    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
+    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 #endif
     mmio_writelen(opaque, addr, value, 0);
 }
@@ -174,7 +175,7 @@ static void mmio_writew (void *opaque,
                          target_phys_addr_t addr, uint32_t value)
 {
 #if defined(DEBUG_MMIO)
-    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
+    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 #endif
     mmio_writelen(opaque, addr, value, 1);
 }
@@ -192,7 +193,7 @@ static void mmio_writel (void *opaque,
                          target_phys_addr_t addr, uint32_t value)
 {
 #if defined(DEBUG_MMIO)
-    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
+    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 #endif
     mmio_writelen(opaque, addr, value, 2);
 }
@@ -214,7 +215,7 @@ int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
                           CPUReadMemoryFunc **mem_read,
                           CPUWriteMemoryFunc **mem_write, void *opaque)
 {
-    uint32_t end;
+    target_phys_addr_t end;
     int idx, eidx;
 
     if ((offset + len) > TARGET_PAGE_SIZE)
@@ -223,8 +224,8 @@ int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
     end = offset + len - 1;
     eidx = MMIO_IDX(end);
 #if defined(DEBUG_MMIO)
-    printf("%s: offset %08x len %08x %08x %d %d\n", __func__, offset, len,
-           end, idx, eidx);
+    printf("%s: offset " PADDRX " len %08" PRIx32 " " PADDRX " %d %d\n",
+           __func__, offset, len, end, idx, eidx);
 #endif
     for (; idx <= eidx; idx++) {
         mmio->mem_read[idx] = mem_read;
@@ -245,8 +246,8 @@ ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
         mmio->base = base;
         mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
 #if defined(DEBUG_MMIO)
-        printf("%s: %p base %08x len %08x %d\n", __func__,
-               mmio, base, TARGET_PAGE_SIZE, mmio_memory);
+        printf("%s: base " PADDRX " len %08x %d\n", __func__,
+               base, TARGET_PAGE_SIZE, mmio_memory);
 #endif
         cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
         ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
@@ -297,9 +298,10 @@ static void ppcuic_trigger_irq (ppcuic_t *uic)
     cr = uic->uicsr & uic->uicer & uic->uiccr;
 #ifdef DEBUG_UIC
     if (loglevel & CPU_LOG_INT) {
-        fprintf(logfile, "%s: uicsr %08x uicer %08x uiccr %08x\n"
-                "   %08x ir %08x cr %08x\n", __func__,
-                uic->uicsr, uic->uicer, uic->uiccr,
+        fprintf(logfile, "%s: uicsr %08" PRIx32 " uicer %08" PRIx32
+                " uiccr %08" PRIx32 "\n"
+                "   %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
+                __func__, uic->uicsr, uic->uicer, uic->uiccr,
                 uic->uicsr & uic->uicer, ir, cr);
     }
 #endif
@@ -342,8 +344,8 @@ static void ppcuic_trigger_irq (ppcuic_t *uic)
         }
 #ifdef DEBUG_UIC
         if (loglevel & CPU_LOG_INT) {
-            fprintf(logfile, "Raise UIC critical interrupt - vector %08x\n",
-                    uic->uicvr);
+            fprintf(logfile, "Raise UIC critical interrupt - "
+                    "vector %08" PRIx32 "\n", uic->uicvr);
         }
 #endif
     } else {
@@ -366,8 +368,9 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
     mask = 1 << irq_num;
 #ifdef DEBUG_UIC
     if (loglevel & CPU_LOG_INT) {
-        fprintf(logfile, "%s: irq %d level %d uicsr %08x mask %08x => %08x "
-                "%08x\n", __func__, irq_num, level,
+        fprintf(logfile, "%s: irq %d level %d uicsr %08" PRIx32
+                " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
+                __func__, irq_num, level,
                 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
     }
 #endif
@@ -392,8 +395,8 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
     }
 #ifdef DEBUG_UIC
     if (loglevel & CPU_LOG_INT) {
-        fprintf(logfile, "%s: irq %d level %d sr %08x => %08x\n", __func__,
-                irq_num, level, uic->uicsr, sr);
+        fprintf(logfile, "%s: irq %d level %d sr %" PRIx32 " => "
+                "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
     }
 #endif
     if (sr != uic->uicsr)
diff --git a/hw/ppc_chrp.c b/hw/ppc_chrp.c
index 9d89b6631a..1e3e6c4f6c 100644
--- a/hw/ppc_chrp.c
+++ b/hw/ppc_chrp.c
@@ -255,7 +255,7 @@ static void ppc_core99_init (int ram_size, int vga_ram_size,
     pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
                  ram_size, vga_ram_size,
                  vga_bios_offset, vga_bios_size);
-    
+
     /* XXX: suppress that */
     dummy_irq = i8259_init(NULL);
 
@@ -274,7 +274,7 @@ static void ppc_core99_init (int ram_size, int vga_ram_size,
 #endif
     /* cuda also initialize ADB */
     cuda_init(&cuda_mem_index, pic[0x19]);
-    
+
     adb_kbd_init(&adb_bus);
     adb_mouse_init(&adb_bus);
 
@@ -314,7 +314,7 @@ static void ppc_core99_init (int ram_size, int vga_ram_size,
 
     /* Special port to get debug messages from Open-Firmware */
     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
- }
+}
 
 QEMUMachine core99_machine = {
     "mac99",
diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
index f3fe1a9d70..53edcd5c66 100644
--- a/hw/ppc_oldworld.c
+++ b/hw/ppc_oldworld.c
@@ -41,7 +41,7 @@ static int vga_osi_call (CPUState *env)
     static int vga_vbl_enabled;
     int linesize;
 
-    //    printf("osi_call R5=%d\n", env->gpr[5]);
+    //    printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5));
 
     /* same handler as PearPC, coming from the original MOL video
        driver. */
@@ -93,7 +93,8 @@ static int vga_osi_call (CPUState *env)
         /* R6 = x, R7 = y, R8 = visible, R9 = data */
         break;
     default:
-        fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]);
+        fprintf(stderr, "unsupported OSI call R5=" REGX "\n",
+                ppc_dump_gpr(env, 5));
         break;
     }
 
@@ -245,7 +246,7 @@ static void ppc_heathrow_init (int ram_size, int vga_ram_size,
     }
 
     isa_mem_base = 0x80000000;
-    
+
     /* Register 2 MB of ISA IO space */
     isa_mmio_init(0xfe000000, 0x00200000);
 
@@ -277,13 +278,13 @@ static void ppc_heathrow_init (int ram_size, int vga_ram_size,
     pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
                  ram_size, vga_ram_size,
                  vga_bios_offset, vga_bios_size);
-    
+
     /* XXX: suppress that */
     dummy_irq = i8259_init(NULL);
 
     /* XXX: use Mac Serial port */
     serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
-    
+
     for(i = 0; i < nb_nics; i++) {
         if (!nd_table[i].model)
             nd_table[i].model = "ne2k_pci";
@@ -301,7 +302,7 @@ static void ppc_heathrow_init (int ram_size, int vga_ram_size,
 
     adb_kbd_init(&adb_bus);
     adb_mouse_init(&adb_bus);
-    
+
     nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
     pmac_format_nvram_partition(nvr, 0x2000);
 
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index d33cf5d9ad..8e939760d3 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -113,7 +113,7 @@ static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
 static void _PPC_intack_write (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
 {
-    //    printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
+//    printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
 }
 
 static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
@@ -122,7 +122,7 @@ static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
 
     if (addr == 0xBFFFFFF0)
         retval = pic_intack_read(isa_pic);
-    //   printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
+//   printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
 
     return retval;
 }
@@ -192,7 +192,7 @@ static struct {
 static void PPC_XCSR_writeb (void *opaque,
                              target_phys_addr_t addr, uint32_t value)
 {
-    printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
+    printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
 }
 
 static void PPC_XCSR_writew (void *opaque,
@@ -201,7 +201,7 @@ static void PPC_XCSR_writew (void *opaque,
 #ifdef TARGET_WORDS_BIGENDIAN
     value = bswap16(value);
 #endif
-    printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
+    printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
 }
 
 static void PPC_XCSR_writel (void *opaque,
@@ -210,14 +210,14 @@ static void PPC_XCSR_writel (void *opaque,
 #ifdef TARGET_WORDS_BIGENDIAN
     value = bswap32(value);
 #endif
-    printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
+    printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
 }
 
 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
 {
     uint32_t retval = 0;
 
-    printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
+    printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
 
     return retval;
 }
@@ -226,7 +226,7 @@ static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
 {
     uint32_t retval = 0;
 
-    printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
+    printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
 #ifdef TARGET_WORDS_BIGENDIAN
     retval = bswap16(retval);
 #endif
@@ -238,7 +238,7 @@ static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
 {
     uint32_t retval = 0;
 
-    printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
+    printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
 #ifdef TARGET_WORDS_BIGENDIAN
     retval = bswap32(retval);
 #endif
@@ -280,7 +280,8 @@ static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
 {
     sysctrl_t *sysctrl = opaque;
 
-    PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
+    PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
+                   val);
     sysctrl->fake_io[addr - 0x0398] = val;
 }
 
@@ -288,7 +289,7 @@ static uint32_t PREP_io_read (void *opaque, uint32_t addr)
 {
     sysctrl_t *sysctrl = opaque;
 
-    PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE,
+    PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
                    sysctrl->fake_io[addr - 0x0398]);
     return sysctrl->fake_io[addr - 0x0398];
 }
@@ -297,7 +298,8 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 {
     sysctrl_t *sysctrl = opaque;
 
-    PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
+    PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
+                   addr - PPC_IO_BASE, val);
     switch (addr) {
     case 0x0092:
         /* Special port 92 */
@@ -353,8 +355,8 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
         sysctrl->contiguous_map = val & 0x01;
         break;
     default:
-        printf("ERROR: unaffected IO port write: %04lx => %02x\n",
-               (long)addr, val);
+        printf("ERROR: unaffected IO port write: %04" PRIx32
+               " => %02" PRIx32"\n", addr, val);
         break;
     }
 }
@@ -416,10 +418,11 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
         retval = sysctrl->contiguous_map;
         break;
     default:
-        printf("ERROR: unaffected IO port: %04lx read\n", (long)addr);
+        printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
         break;
     }
-    PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval);
+    PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
+                   addr - PPC_IO_BASE, retval);
 
     return retval;
 }
@@ -468,7 +471,7 @@ static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
 #ifdef TARGET_WORDS_BIGENDIAN
     value = bswap16(value);
 #endif
-    PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
+    PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
     cpu_outw(NULL, addr, value);
 }
 
@@ -482,7 +485,7 @@ static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
 #ifdef TARGET_WORDS_BIGENDIAN
     ret = bswap16(ret);
 #endif
-    PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
+    PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
 
     return ret;
 }
@@ -496,7 +499,7 @@ static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
 #ifdef TARGET_WORDS_BIGENDIAN
     value = bswap32(value);
 #endif
-    PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
+    PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
     cpu_outl(NULL, addr, value);
 }
 
@@ -510,7 +513,7 @@ static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
 #ifdef TARGET_WORDS_BIGENDIAN
     ret = bswap32(ret);
 #endif
-    PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
+    PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
 
     return ret;
 }