diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2014-10-22 12:06:47 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-10-22 12:06:47 +0100 |
| commit | 31cc9514a50d1dc9fc71aec4e309c8af6fd83f3e (patch) | |
| tree | f0f41fe7b038406b02da8808f68a1e641dd7ab7f /hw | |
| parent | 01a2050fa5fb3d290134b67ee82eb3ebbd91d95b (diff) | |
| parent | 340fff722d8a7cf9c0d4f1e1b4fad03a145a9657 (diff) | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20141015' into staging
* remotes/lalrae/tags/mips-20141015: (28 commits)
target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX
target-mips/dsp_helper.c: Add ifdef guards around various functions
target-mips/translate.c: Add ifdef guard around check_mips64()
target-mips/op_helper.c: Remove unused do_lbu() function
target-mips/dsp_helper.c: Remove unused function get_DSPControl_24()
target-mips: fix broken MIPS16 and microMIPS
target-mips/translate.c: Update OPC_SYNCI
target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA
mips_malta: update malta's pseudo-bootloader - replace JR with JALR
target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions
target-mips: do not allow Status.FR=0 mode in 64-bit FPU
target-mips: add new Floating Point Comparison instructions
target-mips: add new Floating Point instructions
softfloat: add functions corresponding to IEEE-2008 min/maxNumMag
target-mips: add AUI, LSA and PCREL instruction families
target-mips: add compact and CP1 branches
target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions
target-mips: Status.UX/SX/KX enable 32-bit address wrapping
target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6
target-mips: redefine Integer Multiply and Divide instructions
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/mips/mips_malta.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index b20807c4e4..e8e075c600 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -697,12 +697,12 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base, /* Jump to kernel code */ stl_p(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */ stl_p(p++, 0x37ff0000 | (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */ - stl_p(p++, 0x03e00008); /* jr ra */ + stl_p(p++, 0x03e00009); /* jalr ra */ stl_p(p++, 0x00000000); /* nop */ /* YAMON subroutines */ p = (uint32_t *) (base + 0x800); - stl_p(p++, 0x03e00008); /* jr ra */ + stl_p(p++, 0x03e00009); /* jalr ra */ stl_p(p++, 0x24020000); /* li v0,0 */ /* 808 YAMON print */ stl_p(p++, 0x03e06821); /* move t5,ra */ @@ -716,7 +716,7 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base, stl_p(p++, 0x00000000); /* nop */ stl_p(p++, 0x08000205); /* j 814 */ stl_p(p++, 0x00000000); /* nop */ - stl_p(p++, 0x01a00008); /* jr t5 */ + stl_p(p++, 0x01a00009); /* jalr t5 */ stl_p(p++, 0x01602021); /* move a0,t3 */ /* 0x83c YAMON print_count */ stl_p(p++, 0x03e06821); /* move t5,ra */ @@ -730,7 +730,7 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base, stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */ stl_p(p++, 0x1580fffa); /* bnez t4,84c */ stl_p(p++, 0x00000000); /* nop */ - stl_p(p++, 0x01a00008); /* jr t5 */ + stl_p(p++, 0x01a00009); /* jalr t5 */ stl_p(p++, 0x01602021); /* move a0,t3 */ /* 0x870 */ stl_p(p++, 0x3c08b800); /* lui t0,0xb400 */ @@ -740,7 +740,7 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base, stl_p(p++, 0x31290040); /* andi t1,t1,0x40 */ stl_p(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */ stl_p(p++, 0x00000000); /* nop */ - stl_p(p++, 0x03e00008); /* jr ra */ + stl_p(p++, 0x03e00009); /* jalr ra */ stl_p(p++, 0xa1040000); /* sb a0,0(t0) */ } |