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authorArtyom Tarasenko <atar4qemu@gmail.com>2011-07-25 19:22:38 +0200
committerBlue Swirl <blauwirbel@gmail.com>2011-08-28 11:38:13 +0000
commit9f94778c1603420e48d779a495e84eb82945cc75 (patch)
tree735f2ae72f858c7a223b5c34c95578817eb25532 /hw
parent010f3f5fbd5f8edc1a584b5388f8ea2ad518a439 (diff)
Fix disabling interrupts in sun4u
clear interrupt request if the interrupt priority < CPU pil clear hardware interrupt request if interrupts are disabled Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> [blauwirbel@gmail.com: added a comment about magic 2] Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw')
-rw-r--r--hw/sun4u.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 1b60e4ef59..32e6ab9beb 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -261,7 +261,9 @@ void cpu_check_irqs(CPUState *env)
pil |= 1 << 14;
}
- if (!pil) {
+ /* The bit corresponding to psrpil is (1<< psrpil), the next bit
+ is (2 << psrpil). */
+ if (pil < (2 << env->psrpil)){
if (env->interrupt_request & CPU_INTERRUPT_HARD) {
CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
env->interrupt_index);
@@ -293,10 +295,12 @@ void cpu_check_irqs(CPUState *env)
break;
}
}
- } else {
+ } else if (env->interrupt_request & CPU_INTERRUPT_HARD) {
CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
"current interrupt %x\n",
pil, env->pil_in, env->softint, env->interrupt_index);
+ env->interrupt_index = 0;
+ cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
}
}