diff options
| author | Sergey Makarov <s.makarov@syntacore.com> | 2024-09-18 17:02:29 +0300 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2024-11-10 11:09:26 +0300 |
| commit | 665754811d0ee65f2a17ad964d4287369fd01be0 (patch) | |
| tree | 7293d329f97baa546ff81ab3921eebe2feff8cd8 /hw | |
| parent | c2773e521d508f4a2a38eccf2dec1ebfc0f9ff57 (diff) | |
hw/intc: Don't clear pending bits on IRQ lowering
According to PLIC specification (chapter 5), there
is only one case, when interrupt is claimed. Fix
PLIC controller to match this behavior.
Signed-off-by: Sergey Makarov <s.makarov@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240918140229.124329-3-s.makarov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
(cherry picked from commit a84be2baa9eca8bc500f866ad943b8f63dc99adf)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/intc/sifive_plic.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index e559f11805..ca4c2de494 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -349,8 +349,10 @@ static void sifive_plic_irq_request(void *opaque, int irq, int level) { SiFivePLICState *s = opaque; - sifive_plic_set_pending(s, irq, level > 0); - sifive_plic_update(s); + if (level > 0) { + sifive_plic_set_pending(s, irq, true); + sifive_plic_update(s); + } } static void sifive_plic_realize(DeviceState *dev, Error **errp) |