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authorpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2007-04-07 01:24:43 +0000
committerpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2007-04-07 01:24:43 +0000
commit544c4be626e8b4a9f5b4845dc181e0674d8cf762 (patch)
treec4badc39d45aefe13645ab912472eff2f6912722 /hw
parente0c84da78c3bc78e9920d99cdca0d111417ecc2f (diff)
Remove dead code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2631 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw')
-rw-r--r--hw/ide.c38
1 files changed, 0 insertions, 38 deletions
diff --git a/hw/ide.c b/hw/ide.c
index 0cd2521737..e608cc5745 100644
--- a/hw/ide.c
+++ b/hw/ide.c
@@ -2590,44 +2590,6 @@ static void piix3_reset(PCIIDEState *d)
pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
}
-void pci_piix_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn)
-{
- PCIIDEState *d;
- uint8_t *pci_conf;
-
- /* register a function 1 of PIIX */
- d = (PCIIDEState *)pci_register_device(bus, "PIIX IDE",
- sizeof(PCIIDEState),
- devfn,
- NULL, NULL);
- d->type = IDE_TYPE_PIIX3;
-
- pci_conf = d->dev.config;
- pci_conf[0x00] = 0x86; // Intel
- pci_conf[0x01] = 0x80;
- pci_conf[0x02] = 0x30;
- pci_conf[0x03] = 0x12;
- pci_conf[0x08] = 0x02; // Step A1
- pci_conf[0x09] = 0x80; // legacy ATA mode
- pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
- pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
- pci_conf[0x0e] = 0x00; // header_type
-
- piix3_reset(d);
-
- pci_register_io_region((PCIDevice *)d, 4, 0x10,
- PCI_ADDRESS_SPACE_IO, bmdma_map);
-
- ide_init2(&d->ide_if[0], hd_table[0], hd_table[1],
- pic_set_irq_new, isa_pic, 14);
- ide_init2(&d->ide_if[2], hd_table[2], hd_table[3],
- pic_set_irq_new, isa_pic, 15);
- ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
- ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
-
- register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d);
-}
-
/* hd_table must contain 4 block drivers */
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn)