diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2019-10-17 18:16:55 +0100 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2019-10-17 18:16:55 +0100 |
commit | d52932ed34e61831f2ca2cdcb217f61605e72f5d (patch) | |
tree | eb96d60ca0496e8fbc975438c058e0de3cb4f469 /hw | |
parent | f22f553efffd083ff624be116726f843a39f1148 (diff) | |
parent | 69edb0f37a52053978de65a81241ef171a6f2396 (diff) |
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging
x86 and machine queue, 2019-10-15
Features:
* Snowridge-v2 (no MPX) CPU model (Xiaoyao Li)
Bug fixes:
* cpu-plug-test: fix device_add for pc/q35 machines (Igor Mammedov)
* Fix legacy guest with xsave panic on older Linux kernel (Bingsong Si)
* Omit all-zeroes entries from KVM CPUID table (Eduardo Habkost)
Cleanups:
* Convert reset handlers to DeviceReset (Philippe Mathieu-Daudé)
* MachineClass::auto_enable_numa field (Tao Xu)
* target/i386/cpu.h cleanups (Tao Xu)
* memory_device_get_free_addr() cleanups (Wei Yang)
# gpg: Signature made Tue 15 Oct 2019 22:35:43 BST
# gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg: issuer "ehabkost@redhat.com"
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6
* remotes/ehabkost/tags/machine-next-pull-request:
target/i386: Add Snowridge-v2 (no MPX) CPU model
i386: Omit all-zeroes entries from KVM CPUID table
i386: Fix legacy guest with xsave panic on host kvm without update cpuid.
target/i386: drop the duplicated definition of cpuid AVX512_VBMI macro
target/i386: clean up comments over 80 chars per line
memory-device: break the loop if tmp exceed the hinted range
memory-device: not necessary to use goto for the last check
hw/misc/vmcoreinfo: Add comment about reset handler
hw/input/lm832x: Convert reset handler to DeviceReset
hw/isa/vt82c686: Convert reset handler to DeviceReset
hw/ide/via82c: Convert reset handler to DeviceReset
hw/ide/sii3112: Convert reset handler to DeviceReset
hw/ide/piix: Convert reset handler to DeviceReset
hw/isa/piix4: Convert reset handler to DeviceReset
hw/acpi/piix4: Convert reset handler to DeviceReset
numa: Introduce MachineClass::auto_enable_numa for implicit NUMA node
tests: cpu-plug-test: fix device_add for pc/q35 machines
tests: add qtest_qmp_device_add_qdict() helper
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/acpi/piix4.c | 7 | ||||
-rw-r--r-- | hw/core/numa.c | 10 | ||||
-rw-r--r-- | hw/ide/piix.c | 9 | ||||
-rw-r--r-- | hw/ide/sii3112.c | 7 | ||||
-rw-r--r-- | hw/ide/via.c | 10 | ||||
-rw-r--r-- | hw/input/lm832x.c | 12 | ||||
-rw-r--r-- | hw/isa/piix4.c | 7 | ||||
-rw-r--r-- | hw/isa/vt82c686.c | 11 | ||||
-rw-r--r-- | hw/mem/memory-device.c | 3 | ||||
-rw-r--r-- | hw/misc/vmcoreinfo.c | 4 | ||||
-rw-r--r-- | hw/ppc/spapr.c | 9 |
11 files changed, 41 insertions, 48 deletions
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 5742c3df87..4e079b39bd 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -27,7 +27,6 @@ #include "hw/pci/pci.h" #include "hw/qdev-properties.h" #include "hw/acpi/acpi.h" -#include "sysemu/reset.h" #include "sysemu/runstate.h" #include "sysemu/sysemu.h" #include "qapi/error.h" @@ -344,9 +343,9 @@ static const VMStateDescription vmstate_acpi = { } }; -static void piix4_reset(void *opaque) +static void piix4_pm_reset(DeviceState *dev) { - PIIX4PMState *s = opaque; + PIIX4PMState *s = PIIX4_PM(dev); PCIDevice *d = PCI_DEVICE(s); uint8_t *pci_conf = d->config; @@ -542,7 +541,6 @@ static void piix4_pm_realize(PCIDevice *dev, Error **errp) s->machine_ready.notify = piix4_pm_machine_ready; qemu_add_machine_init_done_notifier(&s->machine_ready); - qemu_register_reset(piix4_reset, s); piix4_acpi_system_hot_add_init(pci_address_space_io(dev), pci_get_bus(dev), s); @@ -692,6 +690,7 @@ static void piix4_pm_class_init(ObjectClass *klass, void *data) k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; k->revision = 0x03; k->class_id = PCI_CLASS_BRIDGE_OTHER; + dc->reset = piix4_pm_reset; dc->desc = "PM"; dc->vmsd = &vmstate_acpi; dc->props = piix4_pm_properties; diff --git a/hw/core/numa.c b/hw/core/numa.c index 4dfec5c95b..038c96d4ab 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -378,11 +378,17 @@ void numa_complete_configuration(MachineState *ms) * guest tries to use it with that drivers. * * Enable NUMA implicitly by adding a new NUMA node automatically. + * + * Or if MachineClass::auto_enable_numa is true and no NUMA nodes, + * assume there is just one node with whole RAM. */ - if (ms->ram_slots > 0 && ms->numa_state->num_nodes == 0 && - mc->auto_enable_numa_with_memhp) { + if (ms->numa_state->num_nodes == 0 && + ((ms->ram_slots > 0 && + mc->auto_enable_numa_with_memhp) || + mc->auto_enable_numa)) { NumaNodeOptions node = { }; parse_numa_node(ms, &node, &error_abort); + numa_info[0].node_mem = ram_size; } assert(max_numa_nodeid <= MAX_NODES); diff --git a/hw/ide/piix.c b/hw/ide/piix.c index fba6bc8bff..db313dd3b1 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -30,7 +30,6 @@ #include "sysemu/block-backend.h" #include "sysemu/blockdev.h" #include "sysemu/dma.h" -#include "sysemu/reset.h" #include "hw/ide/pci.h" #include "trace.h" @@ -103,9 +102,9 @@ static void bmdma_setup_bar(PCIIDEState *d) } } -static void piix3_reset(void *opaque) +static void piix_ide_reset(DeviceState *dev) { - PCIIDEState *d = opaque; + PCIIDEState *d = PCI_IDE(dev); PCIDevice *pd = PCI_DEVICE(d); uint8_t *pci_conf = pd->config; int i; @@ -154,8 +153,6 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode - qemu_register_reset(piix3_reset, d); - bmdma_setup_bar(d); pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); @@ -247,6 +244,7 @@ static void piix3_ide_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + dc->reset = piix_ide_reset; k->realize = pci_piix_ide_realize; k->exit = pci_piix_ide_exitfn; k->vendor_id = PCI_VENDOR_ID_INTEL; @@ -273,6 +271,7 @@ static void piix4_ide_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + dc->reset = piix_ide_reset; k->realize = pci_piix_ide_realize; k->exit = pci_piix_ide_exitfn; k->vendor_id = PCI_VENDOR_ID_INTEL; diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c index 2181260531..06605d7af2 100644 --- a/hw/ide/sii3112.c +++ b/hw/ide/sii3112.c @@ -15,7 +15,6 @@ #include "qemu/osdep.h" #include "hw/ide/pci.h" #include "qemu/module.h" -#include "sysemu/reset.h" #include "trace.h" #define TYPE_SII3112_PCI "sii3112" @@ -237,9 +236,9 @@ static void sii3112_set_irq(void *opaque, int channel, int level) sii3112_update_irq(s); } -static void sii3112_reset(void *opaque) +static void sii3112_reset(DeviceState *dev) { - SiI3112PCIState *s = opaque; + SiI3112PCIState *s = SII3112_PCI(dev); int i; for (i = 0; i < 2; i++) { @@ -290,7 +289,6 @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp) s->bmdma[i].bus = &s->bus[i]; ide_register_restart_cb(&s->bus[i]); } - qemu_register_reset(sii3112_reset, s); } static void sii3112_pci_class_init(ObjectClass *klass, void *data) @@ -303,6 +301,7 @@ static void sii3112_pci_class_init(ObjectClass *klass, void *data) pd->class_id = PCI_CLASS_STORAGE_RAID; pd->revision = 1; pd->realize = sii3112_pci_realize; + dc->reset = sii3112_reset; dc->desc = "SiI3112A SATA controller"; set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } diff --git a/hw/ide/via.c b/hw/ide/via.c index 7087dc676e..053622bd82 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -29,7 +29,6 @@ #include "migration/vmstate.h" #include "qemu/module.h" #include "sysemu/dma.h" -#include "sysemu/reset.h" #include "hw/ide/pci.h" #include "trace.h" @@ -120,10 +119,10 @@ static void via_ide_set_irq(void *opaque, int n, int level) } } -static void via_ide_reset(void *opaque) +static void via_ide_reset(DeviceState *dev) { - PCIIDEState *d = opaque; - PCIDevice *pd = PCI_DEVICE(d); + PCIIDEState *d = PCI_IDE(dev); + PCIDevice *pd = PCI_DEVICE(dev); uint8_t *pci_conf = pd->config; int i; @@ -172,8 +171,6 @@ static void via_ide_realize(PCIDevice *dev, Error **errp) pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); dev->wmask[PCI_INTERRUPT_LINE] = 0xf; - qemu_register_reset(via_ide_reset, d); - memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops, &d->bus[0], "via-ide0-data", 8); pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]); @@ -229,6 +226,7 @@ static void via_ide_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + dc->reset = via_ide_reset; k->realize = via_ide_realize; k->exit = via_ide_exitfn; k->vendor_id = PCI_VENDOR_ID_VIA; diff --git a/hw/input/lm832x.c b/hw/input/lm832x.c index a37eb854b9..aa629ddbf1 100644 --- a/hw/input/lm832x.c +++ b/hw/input/lm832x.c @@ -24,7 +24,6 @@ #include "migration/vmstate.h" #include "qemu/module.h" #include "qemu/timer.h" -#include "sysemu/reset.h" #include "ui/console.h" #define TYPE_LM8323 "lm8323" @@ -94,8 +93,10 @@ static void lm_kbd_gpio_update(LM823KbdState *s) { } -static void lm_kbd_reset(LM823KbdState *s) +static void lm_kbd_reset(DeviceState *dev) { + LM823KbdState *s = LM8323(dev); + s->config = 0x80; s->status = INT_NOINIT; s->acttime = 125; @@ -273,7 +274,7 @@ static void lm_kbd_write(LM823KbdState *s, int reg, int byte, uint8_t value) case LM832x_CMD_RESET: if (value == 0xaa) - lm_kbd_reset(s); + lm_kbd_reset(DEVICE(s)); else lm_kbd_error(s, ERR_BADPAR); s->reg = LM832x_GENERAL_ERROR; @@ -476,10 +477,6 @@ static void lm8323_realize(DeviceState *dev, Error **errp) s->pwm.tm[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm1_tick, s); s->pwm.tm[2] = timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm2_tick, s); qdev_init_gpio_out(dev, &s->nirq, 1); - - lm_kbd_reset(s); - - qemu_register_reset((void *) lm_kbd_reset, s); } void lm832x_key_event(DeviceState *dev, int key, int state) @@ -507,6 +504,7 @@ static void lm8323_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); + dc->reset = lm_kbd_reset; dc->realize = lm8323_realize; k->event = lm_i2c_event; k->recv = lm_i2c_rx; diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 3294056cd5..890d999abf 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -28,7 +28,6 @@ #include "hw/isa/isa.h" #include "hw/sysbus.h" #include "migration/vmstate.h" -#include "sysemu/reset.h" PCIDevice *piix4_dev; @@ -40,9 +39,9 @@ typedef struct PIIX4State { #define PIIX4_PCI_DEVICE(obj) \ OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE) -static void piix4_reset(void *opaque) +static void piix4_isa_reset(DeviceState *dev) { - PIIX4State *d = opaque; + PIIX4State *d = PIIX4_PCI_DEVICE(dev); uint8_t *pci_conf = d->dev.config; pci_conf[0x04] = 0x07; // master, memory and I/O @@ -97,7 +96,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } piix4_dev = &d->dev; - qemu_register_reset(piix4_reset, d); } int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn) @@ -118,6 +116,7 @@ static void piix4_class_init(ObjectClass *klass, void *data) k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; k->class_id = PCI_CLASS_BRIDGE_ISA; + dc->reset = piix4_isa_reset; dc->desc = "ISA bridge"; dc->vmsd = &vmstate_piix4; /* diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 50bd28fa82..616f67f347 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -23,7 +23,6 @@ #include "hw/isa/apm.h" #include "hw/acpi/acpi.h" #include "hw/i2c/pm_smbus.h" -#include "sysemu/reset.h" #include "qemu/module.h" #include "qemu/timer.h" #include "exec/address-spaces.h" @@ -116,11 +115,10 @@ static const MemoryRegionOps superio_ops = { }, }; -static void vt82c686b_reset(void * opaque) +static void vt82c686b_isa_reset(DeviceState *dev) { - PCIDevice *d = opaque; - uint8_t *pci_conf = d->config; - VT82C686BState *vt82c = VT82C686B_DEVICE(d); + VT82C686BState *vt82c = VT82C686B_DEVICE(dev); + uint8_t *pci_conf = vt82c->dev.config; pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | @@ -476,8 +474,6 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp) * But we do not emulate a floppy, so just set it here. */ memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, &vt82c->superio); - - qemu_register_reset(vt82c686b_reset, d); } ISABus *vt82c686b_isa_init(PCIBus *bus, int devfn) @@ -501,6 +497,7 @@ static void via_class_init(ObjectClass *klass, void *data) k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; k->class_id = PCI_CLASS_BRIDGE_ISA; k->revision = 0x40; + dc->reset = vt82c686b_isa_reset; dc->desc = "ISA bridge"; dc->vmsd = &vmstate_via; /* diff --git a/hw/mem/memory-device.c b/hw/mem/memory-device.c index 53953fdc3a..aef148c1d7 100644 --- a/hw/mem/memory-device.c +++ b/hw/mem/memory-device.c @@ -179,13 +179,14 @@ static uint64_t memory_device_get_free_addr(MachineState *ms, range_make_empty(&new); break; } + } else if (range_lob(&tmp) > range_upb(&new)) { + break; } } if (!range_contains_range(&as, &new)) { error_setg(errp, "could not find position in guest address space for " "memory device - memory fragmented due to alignments"); - goto out; } out: g_slist_free(list); diff --git a/hw/misc/vmcoreinfo.c b/hw/misc/vmcoreinfo.c index 326a3ce8f4..a9d718fc23 100644 --- a/hw/misc/vmcoreinfo.c +++ b/hw/misc/vmcoreinfo.c @@ -61,6 +61,10 @@ static void vmcoreinfo_realize(DeviceState *dev, Error **errp) NULL, fw_cfg_vmci_write, s, &s->vmcoreinfo, sizeof(s->vmcoreinfo), false); + /* + * This device requires to register a global reset because it is + * not plugged to a bus (which, as its QOM parent, would reset it). + */ qemu_register_reset(vmcoreinfo_reset, dev); vmcoreinfo_state = s; } diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 514a17ae74..4eb97d3a9b 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -346,14 +346,6 @@ static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt) hwaddr mem_start, node_size; int i, nb_nodes = machine->numa_state->num_nodes; NodeInfo *nodes = machine->numa_state->nodes; - NodeInfo ramnode; - - /* No NUMA nodes, assume there is just one node with whole RAM */ - if (!nb_nodes) { - nb_nodes = 1; - ramnode.node_mem = machine->ram_size; - nodes = &ramnode; - } for (i = 0, mem_start = 0; i < nb_nodes; ++i) { if (!nodes[i].node_mem) { @@ -4430,6 +4422,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) */ mc->numa_mem_align_shift = 28; mc->numa_mem_supported = true; + mc->auto_enable_numa = true; smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; |