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authorBernhard Beschow <shentey@gmail.com>2022-10-22 17:04:29 +0200
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2022-10-31 11:32:07 +0100
commit3ee15e807407defcd774586549a00674d58be970 (patch)
treef565d6a7a2dc0dbc89931ff48804d9e898b50278 /hw
parent05c049f12b88370de7289bf39b14088c7d656caa (diff)
hw/isa/piix3: Add size constraints to rcr_ops
According to the PIIX3 datasheet, the reset control register is one byte in size. Moreover, PIIX4 has it, so add it to PIIX3 as well. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20221022150508.26830-5-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/isa/piix3.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 04895ce2e5..72dbf688d9 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -290,7 +290,11 @@ static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
static const MemoryRegionOps rcr_ops = {
.read = rcr_read,
.write = rcr_write,
- .endianness = DEVICE_LITTLE_ENDIAN
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
};
static void pci_piix3_realize(PCIDevice *dev, Error **errp)