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authorBeniamino Galvani <b.galvani@gmail.com>2014-03-25 19:22:04 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-04-17 21:34:06 +0100
commit1c70aa6264ea7f3d7be6f3acb65a1e0aac8b3944 (patch)
treeb78ff4ad33b28ef60d80d9f3c34351e8dbd5ff08 /hw
parentf727d0e6219e6d5a9f91326f01b85aa563e37bb9 (diff)
allwinner-a10-pic: set vector address when an interrupt is pending
This patch implements proper updating of the vector register which should hold, according to the A10 user manual, the vector address for the interrupt currently active on the CPU IRQ input. Interrupt priority is not implemented at the moment and thus the first pending interrupt is returned. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Li Guang <lig.fnst@cn.fujitsu.com> Message-id: 1395771730-16882-2-git-send-email-b.galvani@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/intc/allwinner-a10-pic.c14
1 files changed, 10 insertions, 4 deletions
diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
index 407d563514..00f3c11b46 100644
--- a/hw/intc/allwinner-a10-pic.c
+++ b/hw/intc/allwinner-a10-pic.c
@@ -23,11 +23,20 @@
static void aw_a10_pic_update(AwA10PICState *s)
{
uint8_t i;
- int irq = 0, fiq = 0;
+ int irq = 0, fiq = 0, pending;
+
+ s->vector = 0;
for (i = 0; i < AW_A10_PIC_REG_NUM; i++) {
irq |= s->irq_pending[i] & ~s->mask[i];
fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i];
+
+ if (!s->vector) {
+ pending = ffs(s->irq_pending[i] & ~s->mask[i]);
+ if (pending) {
+ s->vector = (i * 32 + pending - 1) * 4;
+ }
+ }
}
qemu_set_irq(s->parent_irq, !!irq);
@@ -84,9 +93,6 @@ static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value,
uint8_t index = (offset & 0xc) / 4;
switch (offset) {
- case AW_A10_PIC_VECTOR:
- s->vector = value & ~0x3;
- break;
case AW_A10_PIC_BASE_ADDR:
s->base_addr = value & ~0x3;
case AW_A10_PIC_PROTECT: