Add HPET emulation to qemu (Beth Kon)

This patch adds HPET emulation.  It can be disabled with -disable-hpet.  An hpet
provides a more finely granular clocksource than otherwise available on PC.
This means that latency-dependent applications (e.g. multimedia) will generally
be smoother when using the HPET.

Signed-off-by: Beth Kon <eak@us.ibm.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6081 c046a42c-6fe2-441c-8c8c-71466251a162

7 files changed, 732 insertions, 5 deletions

diff --git a/hw/apic.c b/hw/apic.c
index a2915f8121..f6950ca4d4 100644
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -945,6 +945,13 @@ void ioapic_set_irq(void *opaque, int vector, int level)
 {
     IOAPICState *s = opaque;
 
+    /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
+     * to GSI 2.  GSI maps to ioapic 1-1.  This is not
+     * the cleanest way of doing it but it should work. */
+
+    if (vector == 0)
+        vector = 2;
+
     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
         uint32_t mask = 1 << vector;
         uint64_t entry = s->ioredtbl[vector];
diff --git a/hw/hpet.c b/hw/hpet.c
new file mode 100644
index 0000000000..0dc05620c0
--- /dev/null
+++ b/hw/hpet.c
@@ -0,0 +1,588 @@
+/*
+ *  High Precisition Event Timer emulation
+ *
+ *  Copyright (c) 2007 Alexander Graf
+ *  Copyright (c) 2008 IBM Corporation
+ *
+ *  Authors: Beth Kon <bkon@us.ibm.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * *****************************************************************
+ *
+ * This driver attempts to emulate an HPET device in software.
+ */
+
+#include "hw.h"
+#include "console.h"
+#include "qemu-timer.h"
+#include "hpet_emul.h"
+
+extern void hpet_pit_disable(void);
+extern void hpet_pit_enable(void);
+
+//#define HPET_DEBUG
+#ifdef HPET_DEBUG
+#define dprintf printf
+#else
+#define dprintf(...)
+#endif
+
+static HPETState *hpet_statep;
+
+uint32_t hpet_in_legacy_mode(void)
+{
+    if (hpet_statep)
+        return hpet_statep->config & HPET_CFG_LEGACY;
+    else
+        return 0;
+}
+
+static uint32_t timer_int_route(struct HPETTimer *timer)   
+{
+    uint32_t route;
+    route = (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
+    return route;
+}
+
+static uint32_t hpet_enabled(void)
+{
+    return hpet_statep->config & HPET_CFG_ENABLE;
+}
+
+static uint32_t timer_is_periodic(HPETTimer *t)
+{
+    return t->config & HPET_TN_PERIODIC;
+}
+
+static uint32_t timer_enabled(HPETTimer *t)
+{
+    return t->config & HPET_TN_ENABLE;
+}
+
+static uint32_t hpet_time_after(uint64_t a, uint64_t b)
+{
+    return ((int32_t)(b) - (int32_t)(a) < 0);
+}
+
+static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
+{
+    return ((int64_t)(b) - (int64_t)(a) < 0);
+}
+
+static uint64_t ticks_to_ns(uint64_t value) 
+{
+    return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
+}
+
+static uint64_t ns_to_ticks(uint64_t value) 
+{
+    return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
+}
+
+static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
+{
+    new &= mask;
+    new |= old & ~mask;
+    return new;
+}
+
+static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
+{
+    return (!(old & mask) && (new & mask)); 
+}
+
+static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
+{
+    return ((old & mask) && !(new & mask)); 
+}
+
+static uint64_t hpet_get_ticks(void) 
+{
+    uint64_t ticks;
+    ticks = ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset);
+    return ticks;
+}
+
+/* 
+ * calculate diff between comparator value and current ticks  
+ */
+static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
+{
+    
+    if (t->config & HPET_TN_32BIT) {
+        uint32_t diff, cmp;
+        cmp = (uint32_t)t->cmp;
+        diff = cmp - (uint32_t)current;
+        diff = (int32_t)diff > 0 ? diff : (uint32_t)0;
+        return (uint64_t)diff;
+    } else {
+        uint64_t diff, cmp;
+        cmp = t->cmp;
+        diff = cmp - current;
+        diff = (int64_t)diff > 0 ? diff : (uint64_t)0;
+        return diff;
+    }
+}
+
+static void update_irq(struct HPETTimer *timer)
+{
+    qemu_irq irq;
+    int route;
+
+    if (timer->tn <= 1 && hpet_in_legacy_mode()) {
+        /* if LegacyReplacementRoute bit is set, HPET specification requires
+         * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
+         * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC. 
+         */
+        if (timer->tn == 0) {
+            irq=timer->state->irqs[0];
+        } else
+            irq=timer->state->irqs[8];
+    } else {
+        route=timer_int_route(timer);
+        irq=timer->state->irqs[route];
+    }
+    if (timer_enabled(timer) && hpet_enabled()) {
+        qemu_irq_pulse(irq);
+    }
+}
+
+static void hpet_save(QEMUFile *f, void *opaque)
+{
+    HPETState *s = opaque;
+    int i;
+    qemu_put_be64s(f, &s->config);
+    qemu_put_be64s(f, &s->isr);
+    /* save current counter value */
+    s->hpet_counter = hpet_get_ticks(); 
+    qemu_put_be64s(f, &s->hpet_counter);
+
+    for (i = 0; i < HPET_NUM_TIMERS; i++) {
+        qemu_put_8s(f, &s->timer[i].tn);
+        qemu_put_be64s(f, &s->timer[i].config);
+        qemu_put_be64s(f, &s->timer[i].cmp);
+        qemu_put_be64s(f, &s->timer[i].fsb);
+        qemu_put_be64s(f, &s->timer[i].period);
+        qemu_put_8s(f, &s->timer[i].wrap_flag);
+        if (s->timer[i].qemu_timer) {
+            qemu_put_timer(f, s->timer[i].qemu_timer);
+        }
+    }
+}
+
+static int hpet_load(QEMUFile *f, void *opaque, int version_id)
+{
+    HPETState *s = opaque;
+    int i;
+ 
+    if (version_id != 1)
+        return -EINVAL;
+
+    qemu_get_be64s(f, &s->config);
+    qemu_get_be64s(f, &s->isr);
+    qemu_get_be64s(f, &s->hpet_counter);
+    /* Recalculate the offset between the main counter and guest time */
+    s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
+
+    for (i = 0; i < HPET_NUM_TIMERS; i++) {
+        qemu_get_8s(f, &s->timer[i].tn);
+        qemu_get_be64s(f, &s->timer[i].config);
+        qemu_get_be64s(f, &s->timer[i].cmp);
+        qemu_get_be64s(f, &s->timer[i].fsb);
+        qemu_get_be64s(f, &s->timer[i].period);
+        qemu_get_8s(f, &s->timer[i].wrap_flag);
+        if (s->timer[i].qemu_timer) {
+            qemu_get_timer(f, s->timer[i].qemu_timer);
+        }
+    }
+    return 0;
+}
+
+/* 
+ * timer expiration callback
+ */
+static void hpet_timer(void *opaque)
+{
+    HPETTimer *t = (HPETTimer*)opaque;
+    uint64_t diff;
+
+    uint64_t period = t->period;
+    uint64_t cur_tick = hpet_get_ticks();
+
+    if (timer_is_periodic(t) && period != 0) {
+        if (t->config & HPET_TN_32BIT) {
+            while (hpet_time_after(cur_tick, t->cmp))
+                t->cmp = (uint32_t)(t->cmp + t->period);
+        } else
+            while (hpet_time_after64(cur_tick, t->cmp))
+                t->cmp += period;
+
+        diff = hpet_calculate_diff(t, cur_tick);
+        qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) 
+                       + (int64_t)ticks_to_ns(diff));
+    } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
+        if (t->wrap_flag) {
+            diff = hpet_calculate_diff(t, cur_tick);
+            qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) 
+                           + (int64_t)ticks_to_ns(diff));
+            t->wrap_flag = 0;
+        }
+    }
+    update_irq(t);
+}
+
+static void hpet_set_timer(HPETTimer *t)
+{
+    uint64_t diff;
+    uint32_t wrap_diff;  /* how many ticks until we wrap? */
+    uint64_t cur_tick = hpet_get_ticks();
+    
+    /* whenever new timer is being set up, make sure wrap_flag is 0 */
+    t->wrap_flag = 0;
+    diff = hpet_calculate_diff(t, cur_tick);
+
+    /* hpet spec says in one-shot 32-bit mode, generate an interrupt when 
+     * counter wraps in addition to an interrupt with comparator match.
+     */ 
+    if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
+        wrap_diff = 0xffffffff - (uint32_t)cur_tick;
+        if (wrap_diff < (uint32_t)diff) {
+            diff = wrap_diff;
+            t->wrap_flag = 1; 
+        }
+    }
+    qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) 
+                   + (int64_t)ticks_to_ns(diff));
+}
+
+static void hpet_del_timer(HPETTimer *t)
+{
+    qemu_del_timer(t->qemu_timer);
+}
+
+#ifdef HPET_DEBUG
+static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
+{
+    printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
+    return 0;
+}
+
+static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
+{
+    printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
+    return 0;
+}
+#endif
+
+static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
+{
+    HPETState *s = (HPETState *)opaque;
+    uint64_t cur_tick, index;
+
+    dprintf("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
+    index = addr;
+    /*address range of all TN regs*/
+    if (index >= 0x100 && index <= 0x3ff) {
+        uint8_t timer_id = (addr - 0x100) / 0x20;
+        if (timer_id > HPET_NUM_TIMERS - 1) {
+            printf("qemu: timer id out of range\n");
+            return 0;
+        }
+        HPETTimer *timer = &s->timer[timer_id];
+
+        switch ((addr - 0x100) % 0x20) {
+            case HPET_TN_CFG:
+                return timer->config;
+            case HPET_TN_CFG + 4: // Interrupt capabilities
+                return timer->config >> 32;
+            case HPET_TN_CMP: // comparator register
+                return timer->cmp;
+            case HPET_TN_CMP + 4:
+                return timer->cmp >> 32;
+            case HPET_TN_ROUTE:
+                return timer->fsb >> 32;
+            default:
+                dprintf("qemu: invalid hpet_ram_readl\n");
+                break;
+        }
+    } else {
+        switch (index) {
+            case HPET_ID:
+                return s->capability;
+            case HPET_PERIOD:
+                return s->capability >> 32; 
+            case HPET_CFG:
+                return s->config;
+            case HPET_CFG + 4:
+                dprintf("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
+                return 0;
+            case HPET_COUNTER: 
+                if (hpet_enabled())
+                    cur_tick = hpet_get_ticks();
+                else 
+                    cur_tick = s->hpet_counter;
+                dprintf("qemu: reading counter  = %" PRIx64 "\n", cur_tick);
+                return cur_tick;
+            case HPET_COUNTER + 4:
+                if (hpet_enabled())
+                    cur_tick = hpet_get_ticks();
+                else 
+                    cur_tick = s->hpet_counter;
+                dprintf("qemu: reading counter + 4  = %" PRIx64 "\n", cur_tick);
+                return cur_tick >> 32;
+            case HPET_STATUS:
+                return s->isr;
+            default:
+                dprintf("qemu: invalid hpet_ram_readl\n");
+                break;
+        }
+    }
+    return 0;
+}
+
+#ifdef HPET_DEBUG
+static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr, 
+                            uint32_t value)
+{
+    printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n", 
+           addr, value);
+}
+
+static void hpet_ram_writew(void *opaque, target_phys_addr_t addr, 
+                            uint32_t value)
+{
+    printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n", 
+           addr, value);
+}
+#endif
+
+static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
+                            uint32_t value)
+{
+    int i;
+    HPETState *s = (HPETState *)opaque;
+    uint64_t old_val, new_val, index;
+
+    dprintf("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
+    index = addr;
+    old_val = hpet_ram_readl(opaque, addr);
+    new_val = value;
+
+    /*address range of all TN regs*/
+    if (index >= 0x100 && index <= 0x3ff) {
+        uint8_t timer_id = (addr - 0x100) / 0x20;
+        dprintf("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
+        HPETTimer *timer = &s->timer[timer_id];
+        
+        switch ((addr - 0x100) % 0x20) {
+            case HPET_TN_CFG:
+                dprintf("qemu: hpet_ram_writel HPET_TN_CFG\n");
+                timer->config = hpet_fixup_reg(new_val, old_val, 0x3e4e);
+                if (new_val & HPET_TN_32BIT) {
+                    timer->cmp = (uint32_t)timer->cmp;
+                    timer->period = (uint32_t)timer->period;
+                }
+                if (new_val & HPET_TIMER_TYPE_LEVEL) {
+                    printf("qemu: level-triggered hpet not supported\n");
+                    exit (-1);
+                }
+
+                break;
+            case HPET_TN_CFG + 4: // Interrupt capabilities
+                dprintf("qemu: invalid HPET_TN_CFG+4 write\n");
+                break;
+            case HPET_TN_CMP: // comparator register
+                dprintf("qemu: hpet_ram_writel HPET_TN_CMP \n");
+                if (timer->config & HPET_TN_32BIT)
+                    new_val = (uint32_t)new_val;
+                if (!timer_is_periodic(timer) ||
+                           (timer->config & HPET_TN_SETVAL))
+                    timer->cmp = (timer->cmp & 0xffffffff00000000ULL)
+                                  | new_val;
+                else {
+                    /*
+                     * FIXME: Clamp period to reasonable min value?
+                     * Clamp period to reasonable max value
+                     */
+                    new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
+                    timer->period = (timer->period & 0xffffffff00000000ULL)
+                                     | new_val;
+                }
+                timer->config &= ~HPET_TN_SETVAL;
+                if (hpet_enabled())
+                    hpet_set_timer(timer);
+                break;
+            case HPET_TN_CMP + 4: // comparator register high order
+                dprintf("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
+                if (!timer_is_periodic(timer) ||
+                           (timer->config & HPET_TN_SETVAL))
+                    timer->cmp = (timer->cmp & 0xffffffffULL)
+                                  | new_val << 32;
+                else {
+                    /*
+                     * FIXME: Clamp period to reasonable min value?
+                     * Clamp period to reasonable max value
+                     */
+                    new_val &= (timer->config 
+                                & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
+                    timer->period = (timer->period & 0xffffffffULL)
+                                     | new_val << 32;
+                }
+                timer->config &= ~HPET_TN_SETVAL;
+                if (hpet_enabled())
+                    hpet_set_timer(timer);
+                break;
+            case HPET_TN_ROUTE + 4:
+                dprintf("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
+                break;
+            default:
+                dprintf("qemu: invalid hpet_ram_writel\n");
+                break;
+        }
+        return;
+    } else {
+        switch (index) {
+            case HPET_ID:
+                return;
+            case HPET_CFG:
+                s->config = hpet_fixup_reg(new_val, old_val, 0x3);
+                if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
+                    /* Enable main counter and interrupt generation. */
+                    s->hpet_offset = ticks_to_ns(s->hpet_counter)
+                                     - qemu_get_clock(vm_clock);
+                    for (i = 0; i < HPET_NUM_TIMERS; i++)
+                        if ((&s->timer[i])->cmp != ~0ULL)
+                            hpet_set_timer(&s->timer[i]);
+                }
+                else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
+                    /* Halt main counter and disable interrupt generation. */
+                    s->hpet_counter = hpet_get_ticks(); 
+                    for (i = 0; i < HPET_NUM_TIMERS; i++)
+                        hpet_del_timer(&s->timer[i]);
+                }
+                /* i8254 and RTC are disabled when HPET is in legacy mode */
+                if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
+                    hpet_pit_disable();
+                } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
+                    hpet_pit_enable();
+                }
+                break;
+            case HPET_CFG + 4: 
+                dprintf("qemu: invalid HPET_CFG+4 write \n");
+                break;
+            case HPET_STATUS:
+                /* FIXME: need to handle level-triggered interrupts */
+                break;
+            case HPET_COUNTER:
+               if (hpet_enabled()) 
+                   printf("qemu: Writing counter while HPET enabled!\n"); 
+               s->hpet_counter = (s->hpet_counter & 0xffffffff00000000ULL) 
+                                  | value;
+               dprintf("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
+                        value, s->hpet_counter);
+               break;
+            case HPET_COUNTER + 4:
+               if (hpet_enabled()) 
+                   printf("qemu: Writing counter while HPET enabled!\n"); 
+               s->hpet_counter = (s->hpet_counter & 0xffffffffULL) 
+                                  | (((uint64_t)value) << 32);
+               dprintf("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
+                        value, s->hpet_counter);
+               break;
+            default:
+               dprintf("qemu: invalid hpet_ram_writel\n");
+               break;
+        }
+    }
+}
+
+static CPUReadMemoryFunc *hpet_ram_read[] = {
+#ifdef HPET_DEBUG
+    hpet_ram_readb,
+    hpet_ram_readw,
+#else
+    NULL,
+    NULL,
+#endif
+    hpet_ram_readl,
+};
+
+static CPUWriteMemoryFunc *hpet_ram_write[] = {
+#ifdef HPET_DEBUG
+    hpet_ram_writeb,
+    hpet_ram_writew,
+#else
+    NULL,
+    NULL,
+#endif
+    hpet_ram_writel,
+};
+
+static void hpet_reset(void *opaque) {
+    HPETState *s = opaque;
+    int i;
+    static int count = 0;
+
+    for (i=0; i<HPET_NUM_TIMERS; i++) {
+        HPETTimer *timer = &s->timer[i];
+        hpet_del_timer(timer);
+        timer->tn = i;
+        timer->cmp = ~0ULL;
+        timer->config =  HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
+        /* advertise availability of irqs 5,10,11 */
+        timer->config |=  0x00000c20ULL << 32;
+        timer->state = s;
+        timer->period = 0ULL;
+        timer->wrap_flag = 0;
+    }
+
+    s->hpet_counter = 0ULL;
+    s->hpet_offset = 0ULL;
+    /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
+    s->capability = 0x8086a201ULL;
+    s->capability |= ((HPET_CLK_PERIOD) << 32);
+    if (count > 0)
+        /* we don't enable pit when hpet_reset is first called (by hpet_init) 
+         * because hpet is taking over for pit here. On subsequent invocations,
+         * hpet_reset is called due to system reset. At this point control must
+         * be returned to pit until SW reenables hpet.                    
+         */
+        hpet_pit_enable();
+    count = 1;
+}
+
+
+void hpet_init(qemu_irq *irq) {
+    int i, iomemtype;
+    HPETState *s;
+    
+    dprintf ("hpet_init\n");
+
+    s = qemu_mallocz(sizeof(HPETState));
+    hpet_statep = s;
+    s->irqs = irq;
+    for (i=0; i<HPET_NUM_TIMERS; i++) {
+        HPETTimer *timer = &s->timer[i];
+        timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer);
+    }
+    hpet_reset(s);
+    register_savevm("hpet", -1, 1, hpet_save, hpet_load, s);
+    qemu_register_reset(hpet_reset, s);
+    /* HPET Area */
+    iomemtype = cpu_register_io_memory(0, hpet_ram_read,
+                                       hpet_ram_write, s);
+    cpu_register_physical_memory(HPET_BASE, 0x400, iomemtype);
+}
diff --git a/hw/hpet_emul.h b/hw/hpet_emul.h
new file mode 100644
index 0000000000..93a277e263
--- /dev/null
+++ b/hw/hpet_emul.h
@@ -0,0 +1,85 @@
+/*
+ * QEMU Emulated HPET support
+ *
+ * Copyright IBM, Corp. 2008
+ *
+ * Authors:
+ *  Beth Kon   <bkon@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ *
+ */
+#ifndef QEMU_HPET_EMUL_H
+#define QEMU_HPET_EMUL_H
+
+#define HPET_BASE               0xfed00000
+#define HPET_CLK_PERIOD         10000000ULL /* 10000000 femtoseconds == 10ns*/
+
+#define FS_PER_NS 1000000
+#define HPET_NUM_TIMERS 3
+#define HPET_TIMER_TYPE_LEVEL 1
+#define HPET_TIMER_TYPE_EDGE 0
+#define HPET_TIMER_DELIVERY_APIC 0
+#define HPET_TIMER_DELIVERY_FSB 1
+#define HPET_TIMER_CAP_FSB_INT_DEL (1 << 15)
+#define HPET_TIMER_CAP_PER_INT (1 << 4)
+
+#define HPET_CFG_ENABLE 0x001
+#define HPET_CFG_LEGACY 0x002
+
+#define HPET_ID         0x000
+#define HPET_PERIOD     0x004
+#define HPET_CFG        0x010
+#define HPET_STATUS     0x020
+#define HPET_COUNTER    0x0f0
+#define HPET_TN_CFG     0x000
+#define HPET_TN_CMP     0x008
+#define HPET_TN_ROUTE   0x010
+
+
+#define HPET_TN_ENABLE           0x004
+#define HPET_TN_PERIODIC         0x008
+#define HPET_TN_PERIODIC_CAP     0x010
+#define HPET_TN_SIZE_CAP         0x020
+#define HPET_TN_SETVAL           0x040
+#define HPET_TN_32BIT            0x100
+#define HPET_TN_INT_ROUTE_MASK  0x3e00
+#define HPET_TN_INT_ROUTE_SHIFT      9
+#define HPET_TN_INT_ROUTE_CAP_SHIFT 32
+#define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U
+
+struct HPETState;
+typedef struct HPETTimer {  /* timers */
+    uint8_t tn;             /*timer number*/
+    QEMUTimer *qemu_timer;
+    struct HPETState *state;
+    /* Memory-mapped, software visible timer registers */
+    uint64_t config;        /* configuration/cap */
+    uint64_t cmp;           /* comparator */
+    uint64_t fsb;           /* FSB route, not supported now */
+    /* Hidden register state */
+    uint64_t period;        /* Last value written to comparator */
+    uint8_t wrap_flag;      /* timer pop will indicate wrap for one-shot 32-bit 
+                             * mode. Next pop will be actual timer expiration.
+                             */ 
+} HPETTimer;
+
+typedef struct HPETState {
+    uint64_t hpet_offset;
+    qemu_irq *irqs;
+    HPETTimer timer[HPET_NUM_TIMERS];
+
+    /* Memory-mapped, software visible registers */
+    uint64_t capability;        /* capabilities */
+    uint64_t config;            /* configuration */
+    uint64_t isr;               /* interrupt status reg */
+    uint64_t hpet_counter;      /* main counter */
+} HPETState;
+
+#if defined TARGET_I386 || defined TARGET_X86_64
+extern uint32_t hpet_in_legacy_mode(void);
+extern void hpet_init(qemu_irq *irq);
+#endif
+
+#endif
diff --git a/hw/i8254.c b/hw/i8254.c
index 4813b0374c..16257872d9 100644
--- a/hw/i8254.c
+++ b/hw/i8254.c
@@ -463,6 +463,27 @@ static void pit_reset(void *opaque)
     }
 }
 
+/* When HPET is operating in legacy mode, i8254 timer0 is disabled */
+void hpet_pit_disable(void) {
+    PITChannelState *s;
+    s = &pit_state.channels[0];
+    qemu_del_timer(s->irq_timer);
+}
+
+/* When HPET is reset or leaving legacy mode, it must reenable i8254 
+ * timer 0
+ */
+
+void hpet_pit_enable(void)
+{
+    PITState *pit = &pit_state;
+    PITChannelState *s;
+    s = &pit->channels[0];
+    s->mode = 3;
+    s->gate = 1;
+    pit_load_count(s, 0);
+}
+
 PITState *pit_init(int base, qemu_irq irq)
 {
     PITState *pit = &pit_state;
diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c
index ac41a947b8..d25b52b4d3 100644
--- a/hw/mc146818rtc.c
+++ b/hw/mc146818rtc.c
@@ -26,6 +26,7 @@
 #include "sysemu.h"
 #include "pc.h"
 #include "isa.h"
+#include "hpet_emul.h"
 
 //#define DEBUG_CMOS
 
@@ -69,6 +70,18 @@ struct RTCState {
     QEMUTimer *second_timer2;
 };
 
+static void rtc_irq_raise(qemu_irq irq) {
+    /* When HPET is operating in legacy mode, RTC interrupts are disabled 
+     * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
+     * mode is established while interrupt is raised. We want it to 
+     * be lowered in any case
+     */ 
+#if defined TARGET_I386 || defined TARGET_X86_64
+    if (!hpet_in_legacy_mode()) 
+#endif
+        qemu_irq_raise(irq);
+}
+
 static void rtc_set_time(RTCState *s);
 static void rtc_copy_date(RTCState *s);
 
@@ -78,8 +91,14 @@ static void rtc_timer_update(RTCState *s, int64_t current_time)
     int64_t cur_clock, next_irq_clock;
 
     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
-    if (period_code != 0 &&
-        (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
+#if defined TARGET_I386 || defined TARGET_X86_64
+    /* disable periodic timer if hpet is in legacy mode, since interrupts are 
+     * disabled anyway.
+     */
+    if (period_code != 0 && (s->cmos_data[RTC_REG_B] & REG_B_PIE) && !hpet_in_legacy_mode()) {
+#else
+    if (period_code != 0 && (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
+#endif
         if (period_code <= 2)
             period_code += 7;
         /* period in 32 Khz cycles */
@@ -100,7 +119,7 @@ static void rtc_periodic_timer(void *opaque)
 
     rtc_timer_update(s, s->next_periodic_time);
     s->cmos_data[RTC_REG_C] |= 0xc0;
-    qemu_irq_raise(s->irq);
+    rtc_irq_raise(s->irq);
 }
 
 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
@@ -319,14 +338,14 @@ static void rtc_update_second2(void *opaque)
              s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
 
             s->cmos_data[RTC_REG_C] |= 0xa0;
-            qemu_irq_raise(s->irq);
+            rtc_irq_raise(s->irq);
         }
     }
 
     /* update ended interrupt */
     if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
         s->cmos_data[RTC_REG_C] |= 0x90;
-        qemu_irq_raise(s->irq);
+        rtc_irq_raise(s->irq);
     }
 
     /* clear update in progress bit */
diff --git a/hw/pc.c b/hw/pc.c
index fe03704288..64c08a4342 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -35,6 +35,7 @@
 #include "fw_cfg.h"
 #include "virtio-blk.h"
 #include "virtio-balloon.h"
+#include "hpet_emul.h"
 
 /* output Bochs bios info messages */
 //#define DEBUG_BIOS
@@ -977,6 +978,9 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
     }
     pit = pit_init(0x40, i8259[0]);
     pcspk_init(pit);
+    if (!no_hpet) {
+        hpet_init(i8259);
+    }
     if (pci_enabled) {
         pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
     }
diff --git a/hw/pc.h b/hw/pc.h
index b0b8970496..8433084221 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -97,6 +97,9 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
 void acpi_bios_init(void);
 
+/* hpet.c */
+extern int no_hpet;
+
 /* pcspk.c */
 void pcspk_init(PITState *);
 int pcspk_audio_init(AudioState *, qemu_irq *pic);