diff options
| author | Philippe Mathieu-Daudé <philmd@redhat.com> | 2021-03-10 00:27:18 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@redhat.com> | 2021-03-18 11:16:31 +0100 |
| commit | 7d1df53f14a26fa95ebee9767d3a4fac281fd70f (patch) | |
| tree | c76044b3216e69c306143b56b9a0d0000d39b0ae /hw | |
| parent | 7cb1096021fa749f9dc50a3ff074c2101680741c (diff) | |
hw/block/pflash_cfi02: Factor out pflash_reset_state_machine()
There is multiple places resetting the internal state machine.
Factor the code out in a new pflash_reset_state_machine() method.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: David Edmondson <david.edmondson@oracle.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20210310170528.1184868-8-philmd@redhat.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/block/pflash_cfi02.c | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index 2ba77a0171..aea47a99c6 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -184,11 +184,17 @@ static void pflash_setup_mappings(PFlashCFI02 *pfl) pfl->rom_mode = true; } -static void pflash_mode_read_array(PFlashCFI02 *pfl) +static void pflash_reset_state_machine(PFlashCFI02 *pfl) { - trace_pflash_mode_read_array(); + trace_pflash_reset(); pfl->cmd = 0x00; pfl->wcycle = 0; +} + +static void pflash_mode_read_array(PFlashCFI02 *pfl) +{ + trace_pflash_mode_read_array(); + pflash_reset_state_machine(pfl); pfl->rom_mode = true; memory_region_rom_device_set_romd(&pfl->orig_mem, true); } @@ -330,8 +336,7 @@ static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width) default: /* This should never happen : reset state & treat it as a read*/ DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); - pfl->wcycle = 0; - pfl->cmd = 0; + pflash_reset_state_machine(pfl); /* fall through to the read code */ case 0x80: /* Erase (unlock) */ /* We accept reads during second unlock sequence... */ @@ -669,8 +674,7 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value, } reset_dq3(pfl); timer_del(&pfl->timer); - pfl->wcycle = 0; - pfl->cmd = 0; + pflash_reset_state_machine(pfl); return; } /* @@ -710,10 +714,8 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value, /* Reset flash */ reset_flash: - trace_pflash_reset(); pfl->bypass = 0; - pfl->wcycle = 0; - pfl->cmd = 0; + pflash_reset_state_machine(pfl); return; do_bypass: |