diff options
author | Nathan Froyd <froydnj@codesourcery.com> | 2012-06-07 15:04:14 +0000 |
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committer | Blue Swirl <blauwirbel@gmail.com> | 2012-08-09 18:36:19 +0000 |
commit | f1cb0951c5298753652a73cfd8efc0b1a82f37de (patch) | |
tree | 49b9bbe429139f35dd405a554354f53e9c1d5453 /hw/xtensa_lx60.c | |
parent | 832a226b62c6bf75c57ec3ae4d6964923d2aabcd (diff) |
MIPS: Correct FCR0 initialization
This change addresses a problem where QEMU incorrectly traps on
floating-point MADD group instructions with SIGILL, at least while
emulating MIPS32r2 processors. These instructions use the COP1X major
opcode and include ones like:
madd.d $f2,$f4,$f2,$f6
Here's Nathan's original analysis of the problem:
"QEMU essentially does:
d = find_cpu (cpu_string) // get CPU definition
fpu_init (env, d) // initialize fpu state (init FCR0, basically)
cpu_reset (env)
...and the cpu_reset call clears all interesting state that fpu_init
setup, then proceeds to reinitialize all the CP0 registers...but not
FCR0."
I have verified this change with system emulation running the GDB test
suite for the mips-sde-elf target (o32, big endian, 24Kf CPU emulated),
there were 55 progressions and no regressions.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw/xtensa_lx60.c')
0 files changed, 0 insertions, 0 deletions