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authorMax Filippov <jcmvbkbc@gmail.com>2020-07-05 17:31:59 -0700
committerMax Filippov <jcmvbkbc@gmail.com>2020-08-21 12:48:14 -0700
commita7d479ee51c5911c93ee931efe4c2413b54c8756 (patch)
treeb20ef102ab90ee39b39f71df5208f08899bf5c42 /hw/xtensa
parent91dc2b2d12a0343f37a3ab425f2912ae0ce18187 (diff)
target/xtensa: implement NMI support
When NMI is configured it is taken regardless of INTENABLE SR contents, PS.INTLEVEL or PS.EXCM. It is cleared automatically once it's taken. Add nmi_level to XtensaConfig, puth there NMI level from the overlay or XCHAL_NUM_INTLEVELS + 1 when NMI is not configured. Add NMI mask to INTENABLE SR and limit CINTLEVEL to nmi_level - 1 when determining pending IRQ level in check_interrupt(). Always take and clear pending interrupt at nmi_level in the handle_interrupt(). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'hw/xtensa')
-rw-r--r--hw/xtensa/pic_cpu.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/hw/xtensa/pic_cpu.c b/hw/xtensa/pic_cpu.c
index edd53c9241..1d5982a9e4 100644
--- a/hw/xtensa/pic_cpu.c
+++ b/hw/xtensa/pic_cpu.c
@@ -35,9 +35,13 @@ void check_interrupts(CPUXtensaState *env)
{
CPUState *cs = env_cpu(env);
int minlevel = xtensa_get_cintlevel(env);
- uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];
+ uint32_t int_set_enabled = env->sregs[INTSET] &
+ (env->sregs[INTENABLE] | env->config->inttype_mask[INTTYPE_NMI]);
int level;
+ if (minlevel >= env->config->nmi_level) {
+ minlevel = env->config->nmi_level - 1;
+ }
for (level = env->config->nlevel; level > minlevel; --level) {
if (env->config->level_mask[level] & int_set_enabled) {
env->pending_irq_level = level;