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authorDavid Gibson <david@gibson.dropbear.id.au>2012-10-29 17:24:59 +0000
committerAlexander Graf <agraf@suse.de>2012-11-01 13:02:22 +0100
commit3030442054e04b2538016920f0da6e94743f48be (patch)
tree468059237666045da5a2771e7336a1118552b77b /hw/xics.c
parentac7d12ba256b7c9d4e122d0d6877e2312d6c19ed (diff)
target-ppc: Extend FPU state for newer POWER CPUs
This patch adds some extra FPU state to CPUPPCState. Specifically, fpscr is extended to a target_ulong bits, since some recent (64 bit) CPUs now have more status bits than fit inside 32 bits. Also, we add the 32 VSR registers present on CPUs with VSX (these extend the standard FP regs, which together with the Altivec/VMX registers form a 64 x 128bit register file for VSX). We don't actually support the instructions using these extra registers in TCG yet, but we still need a place to store the state so we can sync it with KVM and savevm/loadvm it. This patch updates the savevm code to not fail on the extended state, but also does not actually save it - that's a project for another patch. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
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