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authorAxel Heider <axel.heider@hensoldt.net>2022-10-25 20:32:30 +0200
committerPeter Maydell <peter.maydell@linaro.org>2023-01-05 12:14:43 +0000
commit2ca267fd36a275c771528bd5ae50ae8406155ad9 (patch)
tree8dcbbe806fb97a5657f94767414ddc0396196d3a /hw/timer
parent1ead962edf1297e223a039167429d4c986bfb90e (diff)
hw/timer/imx_epit: update interrupt state on CR write access
The interrupt state can change due to: - reset clears both SR.OCIF and CR.OCIE - write to CR.EN or CR.OCIE Signed-off-by: Axel Heider <axel.heider@hensoldt.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/timer')
-rw-r--r--hw/timer/imx_epit.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index f148868b8c..7af3a8b10e 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -206,12 +206,20 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
if (s->cr & CR_SWR) {
/* handle the reset */
imx_epit_reset(DEVICE(s));
- /*
- * TODO: could we 'break' here? following operations appear
- * to duplicate the work imx_epit_reset() already did.
- */
}
+ /*
+ * The interrupt state can change due to:
+ * - reset clears both SR.OCIF and CR.OCIE
+ * - write to CR.EN or CR.OCIE
+ */
+ imx_epit_update_int(s);
+
+ /*
+ * TODO: could we 'break' here for reset? following operations appear
+ * to duplicate the work imx_epit_reset() already did.
+ */
+
ptimer_transaction_begin(s->timer_cmp);
ptimer_transaction_begin(s->timer_reload);