diff options
author | Artyom Tarasenko <atar4qemu@gmail.com> | 2016-03-02 15:26:08 +0100 |
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committer | Artyom Tarasenko <atar4qemu@gmail.com> | 2017-01-18 22:03:44 +0100 |
commit | a0e893039cf2ce0aacbc8959bc4201cdd192986c (patch) | |
tree | 25fd3ec36c97856875027d2ee5fee81bab5edafb /hw/timer/sun4v-rtc.c | |
parent | 3390537b5df4014e24a30f9bdcfa05c2bd0cd6d8 (diff) |
target-sparc: implement sun4v RTC
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Diffstat (limited to 'hw/timer/sun4v-rtc.c')
-rw-r--r-- | hw/timer/sun4v-rtc.c | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/hw/timer/sun4v-rtc.c b/hw/timer/sun4v-rtc.c new file mode 100644 index 0000000000..82e9e1437b --- /dev/null +++ b/hw/timer/sun4v-rtc.c @@ -0,0 +1,102 @@ +/* + * QEMU sun4v Real Time Clock device + * + * The sun4v_rtc device (sun4v tod clock) + * + * Copyright (c) 2016 Artyom Tarasenko + * + * This code is licensed under the GNU GPL v3 or (at your option) any later + * version. + */ + +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "qemu/timer.h" +#include "hw/timer/sun4v-rtc.h" + +//#define DEBUG_SUN4V_RTC + +#ifdef DEBUG_SUN4V_RTC +#define DPRINTF(fmt, ...) \ + do { printf("sun4v_rtc: " fmt , ## __VA_ARGS__); } while (0) +#else +#define DPRINTF(fmt, ...) do {} while (0) +#endif + +#define TYPE_SUN4V_RTC "sun4v_rtc" +#define SUN4V_RTC(obj) OBJECT_CHECK(Sun4vRtc, (obj), TYPE_SUN4V_RTC) + +typedef struct Sun4vRtc { + SysBusDevice parent_obj; + + MemoryRegion iomem; +} Sun4vRtc; + +static uint64_t sun4v_rtc_read(void *opaque, hwaddr addr, + unsigned size) +{ + uint64_t val = qemu_clock_get_ms(QEMU_CLOCK_REALTIME) / 1000; + if (!(addr & 4ULL)) { + /* accessing the high 32 bits */ + val >>= 32; + } + DPRINTF("read from " TARGET_FMT_plx " val %lx\n", addr, val); + return val; +} + +static void sun4v_rtc_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + DPRINTF("write 0x%x to " TARGET_FMT_plx "\n", (unsigned)val, addr); +} + +static const MemoryRegionOps sun4v_rtc_ops = { + .read = sun4v_rtc_read, + .write = sun4v_rtc_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +void sun4v_rtc_init(hwaddr addr) +{ + DeviceState *dev; + SysBusDevice *s; + + dev = qdev_create(NULL, TYPE_SUN4V_RTC); + s = SYS_BUS_DEVICE(dev); + + qdev_init_nofail(dev); + + sysbus_mmio_map(s, 0, addr); +} + +static int sun4v_rtc_init1(SysBusDevice *dev) +{ + Sun4vRtc *s = SUN4V_RTC(dev); + + memory_region_init_io(&s->iomem, OBJECT(s), &sun4v_rtc_ops, s, + "sun4v-rtc", 0x08ULL); + sysbus_init_mmio(dev, &s->iomem); + return 0; +} + +static void sun4v_rtc_class_init(ObjectClass *klass, void *data) +{ + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + + k->init = sun4v_rtc_init1; +} + +static const TypeInfo sun4v_rtc_info = { + .name = TYPE_SUN4V_RTC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Sun4vRtc), + .class_init = sun4v_rtc_class_init, +}; + +static void sun4v_rtc_register_types(void) +{ + type_register_static(&sun4v_rtc_info); +} + +type_init(sun4v_rtc_register_types) |