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authorPaul Burton <paul.burton@imgtec.com>2013-06-14 08:30:47 +0100
committerAurelien Jarno <aurelien@aurel32.net>2013-07-28 19:59:23 +0200
commit35c648078aa493c3b976840eb7cf2e53ab5b7a2d (patch)
tree24e1e65100ae9ffc5981c4f68652161574bc8d89 /hw/timer/cadence_ttc.c
parent1817f56a834f55311af20d1c004b259c16fb1515 (diff)
mips_malta: generate SMBUS EEPROM data
The malta contains 2 EEPROMs, one containing SPD data for the SDRAM and another containing board information such as serial number and MAC address. These are both exposed via the PIIX4 SMBUS. Generating this data and providing it to smbus_eeprom_init will allow YAMON to read a serial number for the board and prevent it from warning that the EEPROM data is invalid. We already have the contents of the SPD EEPROM which are exposed via FPGA I2C accesses, this is provided as part of the SMBUS EEPROM data too for consistency. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'hw/timer/cadence_ttc.c')
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