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authorBeniamino Galvani <b.galvani@gmail.com>2014-03-25 19:22:07 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-04-17 21:34:06 +0100
commita63f9f85e387791e7a94480379ca5421a0b6d580 (patch)
treec4359bab9c6fd6c1c1864fa492529328297f3a5e /hw/timer/allwinner-a10-pit.c
parent323a8771cfb96ab752c9d27e939a2fbac1380b1c (diff)
allwinner-a10-pit: use level triggered interrupts
Convert the interrupt generation logic to the use of level triggered interrupts. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-5-git-send-email-b.galvani@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/timer/allwinner-a10-pit.c')
-rw-r--r--hw/timer/allwinner-a10-pit.c15
1 files changed, 14 insertions, 1 deletions
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
index 696b7d9977..5aa78a91fd 100644
--- a/hw/timer/allwinner-a10-pit.c
+++ b/hw/timer/allwinner-a10-pit.c
@@ -19,6 +19,15 @@
#include "sysemu/sysemu.h"
#include "hw/timer/allwinner-a10-pit.h"
+static void a10_pit_update_irq(AwA10PITState *s)
+{
+ int i;
+
+ for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
+ qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i)));
+ }
+}
+
static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
{
AwA10PITState *s = AW_A10_PIT(opaque);
@@ -74,9 +83,11 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
switch (offset) {
case AW_A10_PIT_TIMER_IRQ_EN:
s->irq_enable = value;
+ a10_pit_update_irq(s);
break;
case AW_A10_PIT_TIMER_IRQ_ST:
s->irq_status &= ~value;
+ a10_pit_update_irq(s);
break;
case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
index = offset & 0xf0;
@@ -178,6 +189,8 @@ static void a10_pit_reset(DeviceState *dev)
s->irq_enable = 0;
s->irq_status = 0;
+ a10_pit_update_irq(s);
+
for (i = 0; i < 6; i++) {
s->control[i] = AW_A10_PIT_DEFAULT_CLOCK;
s->interval[i] = 0;
@@ -203,7 +216,7 @@ static void a10_pit_timer_cb(void *opaque)
ptimer_stop(s->timer[i]);
s->control[i] &= ~AW_A10_PIT_TIMER_EN;
}
- qemu_irq_pulse(s->irq[i]);
+ a10_pit_update_irq(s);
}
}