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authorChristian Svensson <bluecmd@google.com>2019-09-04 09:05:04 +0200
committerPeter Maydell <peter.maydell@linaro.org>2019-09-13 16:05:01 +0100
commitae275f71338ad4e567c7f2683bf28e66847eabe4 (patch)
treecc93c8a95984aa0de034ffca5ee5e4d0d2add924 /hw/ssi
parent5258c2a69ce6cea0b9ab90f1c83223c0daa8d72c (diff)
aspeed/smc: Calculate checksum on normal DMA
This patch adds the missing checksum calculation on normal DMA transfer. According to the datasheet this is how the SMC should behave. Verified on AST1250 that the hardware matches the behaviour. Signed-off-by: Christian Svensson <bluecmd@google.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190904070506.1052-9-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/ssi')
-rw-r--r--hw/ssi/aspeed_smc.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 5c3436db5e..9ffc7e0117 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -989,6 +989,7 @@ static void aspeed_smc_dma_rw(AspeedSMCState *s)
s->regs[R_DMA_FLASH_ADDR] += 4;
s->regs[R_DMA_DRAM_ADDR] += 4;
s->regs[R_DMA_LEN] -= 4;
+ s->regs[R_DMA_CHECKSUM] += data;
}
}