diff options
| author | Cédric Le Goater <clg@kaod.org> | 2016-10-17 19:22:16 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-10-17 19:22:16 +0100 |
| commit | dcb834447f7b22b08a918e2266e5751035fbfc83 (patch) | |
| tree | 8f121b88f7aba7027a7c6a90fb45531f134654cc /hw/ssi | |
| parent | 0e5803dfbce6cf056fe15b3b5cb31fe8519a6f6e (diff) | |
aspeed: move the flash module mapping address under the controller definition
This will ease the definition of the new controllers for the AST2500
SoC and also ease the support of the segment registers, which provide
a way to reconfigure the mapping window of each slave.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 1474977462-28032-3-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/ssi')
| -rw-r--r-- | hw/ssi/aspeed_smc.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index d319e04a27..84c18299de 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -127,6 +127,10 @@ #define R_SPI_MISC_CTRL (0x10 / 4) #define R_SPI_TIMINGS (0x14 / 4) +#define ASPEED_SOC_SMC_FLASH_BASE 0x10000000 +#define ASPEED_SOC_FMC_FLASH_BASE 0x20000000 +#define ASPEED_SOC_SPI_FLASH_BASE 0x30000000 + /* * Default segments mapping addresses and size for each slave per * controller. These can be changed when board is initialized with the @@ -151,11 +155,14 @@ static const AspeedSegments aspeed_segments_spi[] = { static const AspeedSMCController controllers[] = { { "aspeed.smc.smc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS, - CONF_ENABLE_W0, 5, aspeed_segments_legacy, 0x6000000 }, + CONF_ENABLE_W0, 5, aspeed_segments_legacy, + ASPEED_SOC_SMC_FLASH_BASE, 0x6000000 }, { "aspeed.smc.fmc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS, - CONF_ENABLE_W0, 5, aspeed_segments_fmc, 0x10000000 }, + CONF_ENABLE_W0, 5, aspeed_segments_fmc, + ASPEED_SOC_FMC_FLASH_BASE, 0x10000000 }, { "aspeed.smc.spi", R_SPI_CONF, 0xff, R_SPI_CTRL0, R_SPI_TIMINGS, - SPI_CONF_ENABLE_W0, 1, aspeed_segments_spi, 0x10000000 }, + SPI_CONF_ENABLE_W0, 1, aspeed_segments_spi, + ASPEED_SOC_SPI_FLASH_BASE, 0x10000000 }, }; static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr, @@ -395,7 +402,7 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp) memory_region_init_io(&s->mmio_flash, OBJECT(s), &aspeed_smc_flash_default_ops, s, name, - s->ctrl->mapping_window_size); + s->ctrl->flash_window_size); sysbus_init_mmio(sbd, &s->mmio_flash); s->flashes = g_new0(AspeedSMCFlash, s->num_cs); |