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authorPeter Crosthwaite <peter.crosthwaite@xilinx.com>2013-06-03 17:17:41 +0100
committerPeter Maydell <peter.maydell@linaro.org>2013-06-03 17:17:41 +0100
commit3ea728d0c87011845666caedc582eaa9629797db (patch)
tree4695dbd7e397536779b3372ef363189ee497dcc0 /hw/ssi/xilinx_spips.c
parent87920b44a1e04a45bf74ee0a88a2dfa51c65acdb (diff)
xilinx_spips: Inhibit interrupts in LQSPI mode
The real hardware does not produce interrupts in LQSPI mode. Inhibit generation of interrupts when the LQ_MODE bit is set. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: dff794a06872009ea7e5733ce6adcff94d18bbd0.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/ssi/xilinx_spips.c')
-rw-r--r--hw/ssi/xilinx_spips.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 261d948ba7..a8691d51c4 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -204,6 +204,9 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
static void xilinx_spips_update_ixr(XilinxSPIPS *s)
{
+ if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) {
+ return;
+ }
/* These are set/cleared as they occur */
s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW |
IXR_TX_FIFO_MODE_FAIL);
@@ -256,7 +259,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
for (i = 0; i < num_effective_busses(s); ++i) {
if (!i || s->snoop_state == SNOOP_STRIPING) {
if (fifo8_is_empty(&s->tx_fifo)) {
- s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
+ if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
+ s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
+ }
xilinx_spips_update_ixr(s);
return;
} else {