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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-01-29 21:23:19 +0800
committerPeter Maydell <peter.maydell@linaro.org>2021-02-02 17:00:55 +0000
commitfb116b5456c818ae7c3b788adcbc05dfa416c90c (patch)
treead7cc194350124d3d82a681c274e8f4090492348 /hw/ssi/trace.h
parent7c87bb5333f0fdb17fee7e52acff1d915a68857e (diff)
hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled
When the block is disabled, only the ECSPI_CONREG register can be modified. Setting the EN bit enabled the device, clearing it "disables the block and resets the internal logic with the exception of the ECSPI_CONREG" register. Ignore all other registers write except ECSPI_CONREG when the block is disabled. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210129132323.30946-7-bmeng.cn@gmail.com Message-Id: <20210115153049.3353008-6-f4bug@amsat.org> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/ssi/trace.h')
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