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authorPeter Maydell <peter.maydell@linaro.org>2018-08-24 13:17:46 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-08-24 13:17:46 +0100
commit139d941e5a61d29c895ab422031eb7fd8797e059 (patch)
tree97ee97fbbadf1de2a6ba6aad9599a5a9a85d12c2 /hw/ssi/stm32f2xx_spi.c
parent13391a563fc4048736d259b685676b02dd0ba52d (diff)
hw/ssi/pl022: Correct wrong value for PL022_INT_RT
The PL022 interrupt registers have bits allocated as: 0: ROR (receive overrun) 1: RT (receive timeout) 2: RX (receive FIFO half full or less) 3: TX (transmit FIFO half full or less) A cut and paste error meant we had the wrong value for the PL022_INT_RT constant. This bug doesn't affect device behaviour, because we don't implement the receive timeout feature and so never set that interrupt bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180820141116.9118-20-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/ssi/stm32f2xx_spi.c')
0 files changed, 0 insertions, 0 deletions