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authorCédric Le Goater <clg@kaod.org>2019-07-01 17:26:17 +0100
committerPeter Maydell <peter.maydell@linaro.org>2019-07-01 17:28:59 +0100
commit6da4433fc5fa8aff1096cc651c8d313c70ee6f4d (patch)
tree0ffaad3157d8abb9216a61ca5996a5d95ac38bd7 /hw/ssi/aspeed_smc.c
parentad1a9782186d0ed1c02eb008f268d34599a54a42 (diff)
aspeed/smc: add a 'sdram_base' property
The DRAM address of a DMA transaction depends on the DRAM base address of the SoC. Inform the SMC controller model with this value. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190618165311.27066-15-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/ssi/aspeed_smc.c')
-rw-r--r--hw/ssi/aspeed_smc.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 9eda0d720b..81f2fb7f70 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -913,6 +913,7 @@ static const VMStateDescription vmstate_aspeed_smc = {
static Property aspeed_smc_properties[] = {
DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1),
+ DEFINE_PROP_UINT64("sdram-base", AspeedSMCState, sdram_base, 0),
DEFINE_PROP_END_OF_LIST(),
};