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authorbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2007-05-12 09:19:36 +0000
committerbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2007-05-12 09:19:36 +0000
commita07dec2212d6ba9751dd1dac2b3f4b560325fee0 (patch)
treea6df3df7f76d85b3c592521be006ef909115b918 /hw/spitz.c
parentb645bb48850fea8db017026897827f0ab42fbdea (diff)
Correct NAND erase block size. Misc fixes in Spitz code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2806 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/spitz.c')
-rw-r--r--hw/spitz.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/spitz.c b/hw/spitz.c
index aecace0073..72b049e4e8 100644
--- a/hw/spitz.c
+++ b/hw/spitz.c
@@ -1003,9 +1003,9 @@ static void spitz_common_init(int ram_size, int vga_ram_size,
cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
/* Setup CPU & memory */
- if (ram_size < spitz_ram + spitz_rom) {
+ if (ram_size < spitz_ram + spitz_rom + PXA2XX_INTERNAL_SIZE) {
fprintf(stderr, "This platform requires %i bytes of memory\n",
- spitz_ram + spitz_rom);
+ spitz_ram + spitz_rom + PXA2XX_INTERNAL_SIZE);
exit(1);
}
cpu = pxa270_init(spitz_ram, ds, cpu_model);