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authorPhilippe Mathieu-Daudé <philmd@linaro.org>2023-10-11 15:30:35 +0200
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2023-10-19 23:13:28 +0200
commit4aa07e864911b77dc7fb4704554bb041776b8ec7 (patch)
treedd4bd3ad64aa5132263b72d942017c1c5250105d /hw/sparc64
parentf158d3befe25bef38a2ff364318076466c47a114 (diff)
hw/sparc64/ebus: Access memory regions via pci_address_space_io()
PCI functions are plugged on a PCI bus. They can only access external memory regions via the bus. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231011185954.10337-5-philmd@linaro.org>
Diffstat (limited to 'hw/sparc64')
-rw-r--r--hw/sparc64/sun4u.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index d908a38f73..c871170378 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -360,11 +360,11 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp)
pci_dev->config[0x09] = 0x00; // programming i/f
pci_dev->config[0x0D] = 0x0a; // latency_timer
- memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
- 0, 0x1000000);
+ memory_region_init_alias(&s->bar0, OBJECT(s), "bar0",
+ pci_address_space_io(pci_dev), 0, 0x1000000);
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
- memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
- 0, 0x8000);
+ memory_region_init_alias(&s->bar1, OBJECT(s), "bar1",
+ pci_address_space_io(pci_dev), 0, 0x8000);
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
}