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authorbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2008-12-07 18:49:57 +0000
committerbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2008-12-07 18:49:57 +0000
commitc6d86a33d36891bd5090ea72134b9854d6811173 (patch)
tree67fc4033db10455bf8fcc096de991c130c3a509a /hw/sh_intc.c
parenta4a771c055ea50f255f0d9a555c8628587afbea3 (diff)
sh4: Add IRL (4-bit encoded interrupt input) support (Takashi YOSHII).
This patch adds IRL(4bit encoded 15 level interrupt input) support to SH using qemu_irq as a multi level (!=on/off) signal. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5925 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/sh_intc.c')
-rw-r--r--hw/sh_intc.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/hw/sh_intc.c b/hw/sh_intc.c
index 99db51c6df..b62633d312 100644
--- a/hw/sh_intc.c
+++ b/hw/sh_intc.c
@@ -465,3 +465,18 @@ int sh_intc_init(struct intc_desc *desc,
return 0;
}
+
+/* Assert level <n> IRL interrupt.
+ 0:deassert. 1:lowest priority,... 15:highest priority. */
+void sh_intc_set_irl(void *opaque, int n, int level)
+{
+ struct intc_source *s = opaque;
+ int i, irl = level ^ 15;
+ for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) {
+ if (i == irl)
+ sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1);
+ else
+ if (s->asserted)
+ sh_intc_toggle_source(s, 0, -1);
+ }
+}