Malta CBUS UART support.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2557 c046a42c-6fe2-441c-8c8c-71466251a162

1 files changed, 16 insertions, 13 deletions

diff --git a/hw/serial.c b/hw/serial.c
index a88aec17d1..ed2a857008 100644
--- a/hw/serial.c
+++ b/hw/serial.c
@@ -371,45 +371,45 @@ SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
 }
 
 /* Memory mapped interface */
-static uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
+uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
 {
     SerialState *s = opaque;
 
     return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
 }
 
-static void serial_mm_writeb (void *opaque,
-                              target_phys_addr_t addr, uint32_t value)
+void serial_mm_writeb (void *opaque,
+                       target_phys_addr_t addr, uint32_t value)
 {
     SerialState *s = opaque;
 
     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
 }
 
-static uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
+uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
 {
     SerialState *s = opaque;
 
     return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
 }
 
-static void serial_mm_writew (void *opaque,
-                              target_phys_addr_t addr, uint32_t value)
+void serial_mm_writew (void *opaque,
+                       target_phys_addr_t addr, uint32_t value)
 {
     SerialState *s = opaque;
 
     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
 }
 
-static uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
+uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
 {
     SerialState *s = opaque;
 
     return serial_ioport_read(s, (addr - s->base) >> s->it_shift);
 }
 
-static void serial_mm_writel (void *opaque,
-                              target_phys_addr_t addr, uint32_t value)
+void serial_mm_writel (void *opaque,
+                       target_phys_addr_t addr, uint32_t value)
 {
     SerialState *s = opaque;
 
@@ -430,7 +430,8 @@ static CPUWriteMemoryFunc *serial_mm_write[] = {
 
 SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
                              target_ulong base, int it_shift,
-                             int irq, CharDriverState *chr)
+                             int irq, CharDriverState *chr,
+                             int ioregister)
 {
     SerialState *s;
     int s_io_memory;
@@ -449,9 +450,11 @@ SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
 
     register_savevm("serial", base, 2, serial_save, serial_load, s);
 
-    s_io_memory = cpu_register_io_memory(0, serial_mm_read,
-                                         serial_mm_write, s);
-    cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
+    if (ioregister) {
+        s_io_memory = cpu_register_io_memory(0, serial_mm_read,
+                                             serial_mm_write, s);
+        cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
+    }
     s->chr = chr;
     qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
                           serial_event, s);