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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2018-02-08 13:48:01 -0300
committerPaolo Bonzini <pbonzini@redhat.com>2018-02-13 16:15:08 +0100
commit0540fba949c4d2ed833796a4a23becf5fcc93286 (patch)
tree4e82845e70bfd9f55ccde6bfc8affd767510e41b /hw/sd
parent04654b5a8c8ed5c2fcd77da0c555c936141ee125 (diff)
sdhci: check Spec v2 capabilities (DMA and 64-bit bus)
Incorrect value will throw an error. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-14-f4bug@amsat.org>
Diffstat (limited to 'hw/sd')
-rw-r--r--hw/sd/sdhci-internal.h9
-rw-r--r--hw/sd/sdhci.c19
2 files changed, 19 insertions, 9 deletions
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index f3d54fd4e8..969dbe4ee4 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -91,7 +91,7 @@
#define SDHC_CTRL_HIGH_SPEED 0x04
#define SDHC_CTRL_DMA_CHECK_MASK 0x18
#define SDHC_CTRL_SDMA 0x00
-#define SDHC_CTRL_ADMA1_32 0x08
+#define SDHC_CTRL_ADMA1_32 0x08 /* NOT ALLOWED since v2 */
#define SDHC_CTRL_ADMA2_32 0x10
#define SDHC_CTRL_ADMA2_64 0x18
#define SDHC_DMA_TYPE(x) ((x) & SDHC_CTRL_DMA_CHECK_MASK)
@@ -100,7 +100,6 @@
#define SDHC_CTRL_CDTEST_INS 0x40
#define SDHC_CTRL_CDTEST_EN 0x80
-
/* R/W Power Control Register 0x0 */
#define SDHC_PWRCON 0x29
#define SDHC_POWER_ON (1 << 0)
@@ -190,19 +189,19 @@ FIELD(SDHC_ACMD12ERRSTS, INDEX_ERR, 4, 1);
/* HWInit Capabilities Register 0x05E80080 */
#define SDHC_CAPAB 0x40
-#define SDHC_CAN_DO_ADMA2 0x00080000
-#define SDHC_CAN_DO_ADMA1 0x00100000
-#define SDHC_64_BIT_BUS_SUPPORT (1 << 28)
FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6);
FIELD(SDHC_CAPAB, TOUNIT, 7, 1);
FIELD(SDHC_CAPAB, BASECLKFREQ, 8, 8);
FIELD(SDHC_CAPAB, MAXBLOCKLENGTH, 16, 2);
+FIELD(SDHC_CAPAB, ADMA2, 19, 1); /* since v2 */
+FIELD(SDHC_CAPAB, ADMA1, 20, 1); /* v1 only? */
FIELD(SDHC_CAPAB, HIGHSPEED, 21, 1);
FIELD(SDHC_CAPAB, SDMA, 22, 1);
FIELD(SDHC_CAPAB, SUSPRESUME, 23, 1);
FIELD(SDHC_CAPAB, V33, 24, 1);
FIELD(SDHC_CAPAB, V30, 25, 1);
FIELD(SDHC_CAPAB, V18, 26, 1);
+FIELD(SDHC_CAPAB, BUS64BIT, 28, 1); /* since v2 */
/* HWInit Maximum Current Capabilities Register 0x0 */
#define SDHC_MAXCURR 0x48
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index a6322f20f4..d4a7c68db7 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -89,6 +89,17 @@ static void sdhci_check_capareg(SDHCIState *s, Error **errp)
switch (s->sd_spec_version) {
case 2: /* default version */
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2);
+ trace_sdhci_capareg("ADMA2", val);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0);
+
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1);
+ trace_sdhci_capareg("ADMA1", val);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0);
+
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT);
+ trace_sdhci_capareg("64-bit system bus", val);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0);
/* fallthrough */
case 1:
@@ -832,7 +843,7 @@ static void sdhci_data_transfer(void *opaque)
break;
case SDHC_CTRL_ADMA1_32:
- if (!(s->capareg & SDHC_CAN_DO_ADMA1)) {
+ if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) {
trace_sdhci_error("ADMA1 not supported");
break;
}
@@ -840,7 +851,7 @@ static void sdhci_data_transfer(void *opaque)
sdhci_do_adma(s);
break;
case SDHC_CTRL_ADMA2_32:
- if (!(s->capareg & SDHC_CAN_DO_ADMA2)) {
+ if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) {
trace_sdhci_error("ADMA2 not supported");
break;
}
@@ -848,8 +859,8 @@ static void sdhci_data_transfer(void *opaque)
sdhci_do_adma(s);
break;
case SDHC_CTRL_ADMA2_64:
- if (!(s->capareg & SDHC_CAN_DO_ADMA2) ||
- !(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) {
+ if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) ||
+ !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) {
trace_sdhci_error("64 bit ADMA not supported");
break;
}