diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2018-02-08 13:48:01 -0300 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2018-02-13 16:15:08 +0100 |
| commit | 0540fba949c4d2ed833796a4a23becf5fcc93286 (patch) | |
| tree | 4e82845e70bfd9f55ccde6bfc8affd767510e41b /hw/sd/sdhci-internal.h | |
| parent | 04654b5a8c8ed5c2fcd77da0c555c936141ee125 (diff) | |
sdhci: check Spec v2 capabilities (DMA and 64-bit bus)
Incorrect value will throw an error.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-Id: <20180208164818.7961-14-f4bug@amsat.org>
Diffstat (limited to 'hw/sd/sdhci-internal.h')
| -rw-r--r-- | hw/sd/sdhci-internal.h | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index f3d54fd4e8..969dbe4ee4 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -91,7 +91,7 @@ #define SDHC_CTRL_HIGH_SPEED 0x04 #define SDHC_CTRL_DMA_CHECK_MASK 0x18 #define SDHC_CTRL_SDMA 0x00 -#define SDHC_CTRL_ADMA1_32 0x08 +#define SDHC_CTRL_ADMA1_32 0x08 /* NOT ALLOWED since v2 */ #define SDHC_CTRL_ADMA2_32 0x10 #define SDHC_CTRL_ADMA2_64 0x18 #define SDHC_DMA_TYPE(x) ((x) & SDHC_CTRL_DMA_CHECK_MASK) @@ -100,7 +100,6 @@ #define SDHC_CTRL_CDTEST_INS 0x40 #define SDHC_CTRL_CDTEST_EN 0x80 - /* R/W Power Control Register 0x0 */ #define SDHC_PWRCON 0x29 #define SDHC_POWER_ON (1 << 0) @@ -190,19 +189,19 @@ FIELD(SDHC_ACMD12ERRSTS, INDEX_ERR, 4, 1); /* HWInit Capabilities Register 0x05E80080 */ #define SDHC_CAPAB 0x40 -#define SDHC_CAN_DO_ADMA2 0x00080000 -#define SDHC_CAN_DO_ADMA1 0x00100000 -#define SDHC_64_BIT_BUS_SUPPORT (1 << 28) FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6); FIELD(SDHC_CAPAB, TOUNIT, 7, 1); FIELD(SDHC_CAPAB, BASECLKFREQ, 8, 8); FIELD(SDHC_CAPAB, MAXBLOCKLENGTH, 16, 2); +FIELD(SDHC_CAPAB, ADMA2, 19, 1); /* since v2 */ +FIELD(SDHC_CAPAB, ADMA1, 20, 1); /* v1 only? */ FIELD(SDHC_CAPAB, HIGHSPEED, 21, 1); FIELD(SDHC_CAPAB, SDMA, 22, 1); FIELD(SDHC_CAPAB, SUSPRESUME, 23, 1); FIELD(SDHC_CAPAB, V33, 24, 1); FIELD(SDHC_CAPAB, V30, 25, 1); FIELD(SDHC_CAPAB, V18, 26, 1); +FIELD(SDHC_CAPAB, BUS64BIT, 28, 1); /* since v2 */ /* HWInit Maximum Current Capabilities Register 0x0 */ #define SDHC_MAXCURR 0x48 |